From patchwork Mon Dec 6 09:26:04 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabien Chouteau X-Patchwork-Id: 74328 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CE1EAB70A3 for ; Mon, 6 Dec 2010 20:47:00 +1100 (EST) Received: from localhost ([127.0.0.1]:41283 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PPXer-0001Ie-Ew for incoming@patchwork.ozlabs.org; Mon, 06 Dec 2010 04:46:57 -0500 Received: from [140.186.70.92] (port=37644 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PPXLf-0003KP-NS for qemu-devel@nongnu.org; Mon, 06 Dec 2010 04:27:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PPXLd-0006XY-IV for qemu-devel@nongnu.org; Mon, 06 Dec 2010 04:27:07 -0500 Received: from mel.act-europe.fr ([194.98.77.210]:32853) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PPXLd-0006Qh-7l for qemu-devel@nongnu.org; Mon, 06 Dec 2010 04:27:05 -0500 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 9B042CB029A; Mon, 6 Dec 2010 10:26:43 +0100 (CET) X-Quarantine-ID: X-Virus-Scanned: amavisd-new at eu.adacore.com X-Amavis-Alert: BAD HEADER, Duplicate header field: "In-Reply-To" Received: from mel.act-europe.fr ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id gzDRmqFj8xum; Mon, 6 Dec 2010 10:26:43 +0100 (CET) Received: from PomPomGalli.act-europe.fr (pompomgalli.act-europe.fr [10.10.1.88]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mel.act-europe.fr (Postfix) with ESMTP id 760DACB029D; Mon, 6 Dec 2010 10:26:43 +0100 (CET) From: Fabien Chouteau To: qemu-devel@nongnu.org Date: Mon, 6 Dec 2010 10:26:04 +0100 Message-Id: <5c4895c6f9c6ebd80262c494563726dd59a7ff93.1291397462.git.chouteau@adacore.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: References: In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: Fabien Chouteau Subject: [Qemu-devel] [PATCH 3/6] [RFC] Emulation of GRLIB APB UART as defined in GRLIB IP Core User's Manual. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Fabien Chouteau --- hw/grlib_apbuart.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 231 insertions(+), 0 deletions(-) diff --git a/hw/grlib_apbuart.c b/hw/grlib_apbuart.c new file mode 100644 index 0000000..32a5362 --- /dev/null +++ b/hw/grlib_apbuart.c @@ -0,0 +1,231 @@ +/* + * QEMU GRLIB APB UART Emulator + * + * Copyright (c) 2010 AdaCore + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "sysbus.h" +#include "qemu-char.h" + +#include "grlib.h" + +/* #define DEBUG_UART */ + +#ifdef DEBUG_UART +#define DPRINTF(fmt, ...) \ + do { printf("APBUART: " fmt , ## __VA_ARGS__); } while (0) +#else +#define DPRINTF(fmt, ...) +#endif + +#define UART_REG_SIZE 20 /* Size of memory mapped registers */ + +/* UART status register fields */ +#define UART_DATA_READY (1 << 0) +#define UART_TRANSMIT_SHIFT_EMPTY (1 << 1) +#define UART_TRANSMIT_FIFO_EMPTY (1 << 2) +#define UART_BREAK_RECEIVED (1 << 3) +#define UART_OVERRUN (1 << 4) +#define UART_PARITY_ERROR (1 << 5) +#define UART_FRAMING_ERROR (1 << 6) +#define UART_TRANSMIT_FIFO_HALF (1 << 7) +#define UART_RECEIV_FIFO_HALF (1 << 8) +#define UART_TRANSMIT_FIFO_FULL (1 << 9) +#define UART_RECEIV_FIFO_FULL (1 << 10) + +/* UART control register fields */ +#define UART_RECEIV_ENABLE (1 << 0) +#define UART_TRANSMIT_ENABLE (1 << 1) +#define UART_RECEIV_INTERRUPT (1 << 2) +#define UART_TRANSMIT_INTERRUPT (1 << 3) +#define UART_PARITY_SELECT (1 << 4) +#define UART_PARITY_ENABLE (1 << 5) +#define UART_FLOW_CONTROL (1 << 6) +#define UART_LOOPBACK (1 << 7) +#define UART_EXTERNAL_CLOCK (1 << 8) +#define UART_RECEIV_FIFO_INTERRUPT (1 << 9) +#define UART_TRANSMIT_FIFO_INTERRUPT (1 << 10) +#define UART_FIFO_DEBUG_MODE (1 << 11) +#define UART_OUTPUT_ENABLE (1 << 12) +#define UART_FIFO_AVAILABLE (1 << 31) + +/* Memory mapped register offsets */ +#define DATA_OFFSET 0x00 +#define STATUS_OFFSET 0x04 +#define CONTROL_OFFSET 0x08 +#define SCALER_OFFSET 0x0C /* not supported */ +#define FIFO_DEBUG_OFFSET 0x10 /* not supported */ + +typedef struct UART +{ + SysBusDevice busdev; + + qemu_irq irq; + + CharDriverState *chr; + + /* registers */ + uint32_t receive; + uint32_t status; + uint32_t control; +} UART; + + +DeviceState *grlib_apbuart_create(target_phys_addr_t base, + CharDriverState *serial, + qemu_irq irq) +{ + DeviceState *dev; + + dev = qdev_create(NULL, "grlib,apbuart"); + qdev_prop_set_ptr(dev, "chrdev", serial); + + if (qdev_init(dev)) { + return NULL; + } + + sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); + + sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); + + return dev; +} + +static int grlib_apbuart_can_receive(void *opaque) +{ + UART *uart = opaque; + assert(uart != NULL); + + return !!(uart->status & UART_DATA_READY); +} + +static void grlib_apbuart_receive(void *opaque, const uint8_t *buf, int size) +{ + UART *uart = opaque; + assert(uart != NULL); + + uart->receive = *buf; + uart->status |= UART_DATA_READY; + + if (uart->control & UART_RECEIV_INTERRUPT) + qemu_set_irq(uart->irq, 1); +} + +static void grlib_apbuart_event(void *opaque, int event) +{ +#ifdef DEBUG_UART + printf("uart: event %x\n", event); +#endif +} + +static void +grlib_apbuart_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +{ + UART *uart = opaque; + unsigned char c = 0; + + addr &= 0xff; + + assert(uart != NULL); + + /* Unit registers */ + switch (addr) + { + case DATA_OFFSET: + c = value & 0xFF; + qemu_chr_write(uart->chr, &c, 1); + return; + + case STATUS_OFFSET: + /* Read Only (disable timer freeze not supported) */ + return; + + case CONTROL_OFFSET: + return; + + case SCALER_OFFSET: + /* Not supported */ + return; + + default: + break; + } + + DPRINTF("write unknown register 0x%04x\n", (int)addr); +} + +static CPUReadMemoryFunc *grlib_apbuart_read[] = { + NULL, NULL, NULL, +}; + +static CPUWriteMemoryFunc *grlib_apbuart_write[] = { + NULL, NULL, grlib_apbuart_writel, +}; + +static int grlib_gptimer_init(SysBusDevice *dev) +{ + UART *uart = FROM_SYSBUS(typeof (*uart), dev); + int uart_regs = 0; + + assert(uart != NULL); + assert(uart->chr != NULL); + + qemu_chr_add_handlers(uart->chr, + grlib_apbuart_can_receive, + grlib_apbuart_receive, + grlib_apbuart_event, + uart); + + sysbus_init_irq(dev, &uart->irq); + + uart_regs = cpu_register_io_memory(grlib_apbuart_read, + grlib_apbuart_write, + uart); + if (uart_regs < 0) { + return -1; + } + + sysbus_init_mmio(dev, UART_REG_SIZE, uart_regs); + + return 0; +} + +static SysBusDeviceInfo grlib_gptimer_info = { + .init = grlib_gptimer_init, + .qdev.name = "grlib,apbuart", + .qdev.size = sizeof(UART), + .qdev.props = (Property[]) { + { + .name = "chrdev", + .info = &qdev_prop_ptr, + .offset = offsetof(UART, chr), + .defval = (void*[]) { NULL }, + }, + {/* end of list */} + } +}; + +static void grlib_gptimer_register(void) +{ + sysbus_register_withprop(&grlib_gptimer_info); +} + +device_init(grlib_gptimer_register)