[U-Boot] drivers/mmc/fsl_esdhc: Set the eSHDC DMACTL[SNOOP] bit after the completion of Host Controller reset.

Submitted by P.V.Suresh on Dec. 6, 2010, 5:57 a.m.

Details

Message ID 1291615029-31678-1-git-send-email-pala@freescale.com
State Accepted
Commit 2c1764efc2872fc944d0d580e911168c0a231f8c
Delegated to: Kumar Gala
Headers show

Commit Message

P.V.Suresh Dec. 6, 2010, 5:57 a.m.
eSDHC host controller reset results in clearing of snoop bit also.
This patch sets the SNOOP bit after the completion of host controller reset.
Without this patch mmc reads are not consistent.

Signed-off-by: P.V.Suresh <pala@freescale.com>
---

 This patch applies to master branch of git://git.denx.de/u-boot.git

 drivers/mmc/fsl_esdhc.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

Comments

Kumar Gala Dec. 13, 2010, 3:30 p.m.
On Dec 5, 2010, at 11:57 PM, P.V.Suresh wrote:

> eSDHC host controller reset results in clearing of snoop bit also.
> This patch sets the SNOOP bit after the completion of host controller reset.
> Without this patch mmc reads are not consistent.
> 
> Signed-off-by: P.V.Suresh <pala@freescale.com>
> ---
> 
> This patch applies to master branch of git://git.denx.de/u-boot.git
> 
> drivers/mmc/fsl_esdhc.c |    8 ++++----
> 1 files changed, 4 insertions(+), 4 deletions(-)

applied to 85xx

[shortened the commit one liner]

- k

Patch hide | download patch | download mbox

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index a368fe6..57cd4ee 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -384,10 +384,6 @@  static int esdhc_init(struct mmc *mmc)
 	int ret = 0;
 	u8 card_absent;
 
-	/* Enable cache snooping */
-	if (cfg && !cfg->no_snoop)
-		esdhc_write32(&regs->scr, 0x00000040);
-
 	/* Reset the entire host controller */
 	esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
 
@@ -395,6 +391,10 @@  static int esdhc_init(struct mmc *mmc)
 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
 		udelay(1000);
 
+	/* Enable cache snooping */
+	if (cfg && !cfg->no_snoop)
+		esdhc_write32(&regs->scr, 0x00000040);
+
 	esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 
 	/* Set the initial clock speed */