From patchwork Fri Dec 3 23:08:29 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Carrot Wei X-Patchwork-Id: 74219 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 2ED11B6EED for ; Sat, 4 Dec 2010 10:08:44 +1100 (EST) Received: (qmail 6120 invoked by alias); 3 Dec 2010 23:08:41 -0000 Received: (qmail 6107 invoked by uid 22791); 3 Dec 2010 23:08:40 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, SPF_HELO_PASS, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from smtp-out.google.com (HELO smtp-out.google.com) (216.239.44.51) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Fri, 03 Dec 2010 23:08:33 +0000 Received: from kpbe17.cbf.corp.google.com (kpbe17.cbf.corp.google.com [172.25.105.81]) by smtp-out.google.com with ESMTP id oB3N8UIY003637 for ; Fri, 3 Dec 2010 15:08:30 -0800 Received: from gyg4 (gyg4.prod.google.com [10.243.50.132]) by kpbe17.cbf.corp.google.com with ESMTP id oB3N7pTh004070 for ; Fri, 3 Dec 2010 15:08:29 -0800 Received: by gyg4 with SMTP id 4so5003654gyg.8 for ; Fri, 03 Dec 2010 15:08:29 -0800 (PST) MIME-Version: 1.0 Received: by 10.150.228.10 with SMTP id a10mr4623720ybh.20.1291417709174; Fri, 03 Dec 2010 15:08:29 -0800 (PST) Received: by 10.151.78.4 with HTTP; Fri, 3 Dec 2010 15:08:29 -0800 (PST) In-Reply-To: <116770A4-86FF-49F0-8470-0B7F162DC7FC@buzzard.freeserve.co.uk> References: <201011081155.10464.paul@codesourcery.com> <201011091116.41691.paul@codesourcery.com> <4CE1E761.9060803@gnu.org> <116770A4-86FF-49F0-8470-0B7F162DC7FC@buzzard.freeserve.co.uk> Date: Fri, 3 Dec 2010 15:08:29 -0800 Message-ID: Subject: Re: [PATCH: PR target/44999] Replace "and r0, r0, #255" with uxtb in thumb2 From: Carrot Wei To: Richard Earnshaw Cc: Paolo Bonzini , Paul Brook , "gcc-patches@gcc.gnu.org" , Richard Earnshaw X-System-Of-Record: true Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org On Wed, Dec 1, 2010 at 4:19 PM, Richard Earnshaw wrote: > Please don't try to mix patches for different things. Firstly it makes reviewing harder.  Secondly if there's a problem found after the patch is committed the all the changes may get revered rather than just the change that caused the problem. If one part of a patch is dependent on a separate change then please say so in your submission. > > Now on to the details. > > Uxtb and uxth may generate smaller code, but on cortex-a9 they take longer to execute than AND.  So we most likely only want to do this if either optimising for size or if we can't hoist a constant out of a loop. > Added the condition checking. > What's the justification for the class_likely_spilled change?  I can't immediately see why this constraint is any less likely to be true on thumb2 than on thumb1, since the contents of the class is the same (getting this wrong can cause ICEs). > On thumb1 only low registers can be used in normal alu instructions, but on thumb2 nearly all registers can be used in normal alu instructions. The register usage on thumb2 is more like that on arm instruction set. So I think it should also have the same class_likely_spilled behavior as arm. But anyway I removed it from the patch. thanks Guozhi ChangeLog: 2010-12-03 Wei Guozhi PR target/44999 * config/arm/arm.md (andsi3): Revert it. * config/arm/thumb2.md (thumb2_zero_extendqisi2_v6): Revert it. (split andsi3): New split to convert and with 0xFF to uxtb. ChangeLog: 2010-12-03 Wei Guozhi PR target/44999 * gcc.target/arm/pr44999.c: Update it to more general. Index: thumb2.md =================================================================== --- thumb2.md (revision 165462) +++ thumb2.md (working copy) @@ -585,7 +585,7 @@ (set_attr "neg_pool_range" "*,250")] ) -(define_insn "thumb2_zero_extendqisi2_v6" +(define_insn "*thumb2_zero_extendqisi2_v6" [(set (match_operand:SI 0 "s_register_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,m")))] "TARGET_THUMB2 && arm_arch6" @@ -1118,3 +1118,17 @@ " operands[2] = GEN_INT (32 - INTVAL (operands[2])); ") + +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (and:SI (match_operand:SI 1 "s_register_operand" "") + (match_operand:SI 2 "const_int_operand" "")))] + "TARGET_THUMB2 && arm_arch6 && INTVAL (operands[2]) == 255 + && (optimize_size || !arm_tune_cortex_a9)" + [(set (match_dup 0) + (zero_extend:SI (match_dup 1)))] + " + operands[1] = convert_to_mode (QImode, operands[1], 1); + " +) + Index: arm.md =================================================================== --- arm.md (revision 165462) +++ arm.md (working copy) @@ -2015,17 +2015,9 @@ { if (GET_CODE (operands[2]) == CONST_INT) { - if (INTVAL (operands[2]) == 255 && arm_arch6) - { - operands[1] = convert_to_mode (QImode, operands[1], 1); - emit_insn (gen_thumb2_zero_extendqisi2_v6 (operands[0], - operands[1])); - } - else - arm_split_constant (AND, SImode, NULL_RTX, - INTVAL (operands[2]), operands[0], - operands[1], - optimize && can_create_pseudo_p ()); + arm_split_constant (AND, SImode, NULL_RTX, + INTVAL (operands[2]), operands[0], + operands[1], optimize && can_create_pseudo_p ()); DONE; } Index: pr44999.c =================================================================== --- pr44999.c (revision 165462) +++ pr44999.c (working copy) @@ -5,5 +5,5 @@ int tp(int x, int y) { - return (x & 0xff) - (y & 0xffff); + return ((x+3) & 0xff) - (y & 0xffff); }