clk: tegra: Add UARTB reset

Submitted by Peter De Schrijver on March 22, 2017, 12:58 p.m.

Details

Message ID 1490187493-6162-1-git-send-email-pdeschrijver@nvidia.com
State New
Headers show

Commit Message

Peter De Schrijver March 22, 2017, 12:58 p.m.
Bit 7 of CLK_RST_CONTROLLER_RST_DEVICES_L_0 controls the UARTB reset.
Despite the fact that Tegra210 doesn't have VFIR, 224 was assigned as the
clock ID for UARTB. We can't use 224 as the reset ID because that's already
used for TEGRA210_RST_DFLL_DVCO.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
 include/dt-bindings/reset/tegra210-car.h | 2 ++
 1 file changed, 2 insertions(+)

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diff --git a/include/dt-bindings/reset/tegra210-car.h b/include/dt-bindings/reset/tegra210-car.h
index 296ec6e..de2fce4 100644
--- a/include/dt-bindings/reset/tegra210-car.h
+++ b/include/dt-bindings/reset/tegra210-car.h
@@ -6,6 +6,8 @@ 
 #ifndef _DT_BINDINGS_RESET_TEGRA210_CAR_H
 #define _DT_BINDINGS_RESET_TEGRA210_CAR_H
 
+#define TEGRA210_RST_UARTB		7
+
 #define TEGRA210_RESET(x)		(7 * 32 + (x))
 #define TEGRA210_RST_DFLL_DVCO		TEGRA210_RESET(0)
 #define TEGRA210_RST_ADSP		TEGRA210_RESET(1)