| Message ID | 1490147691-4489-3-git-send-email-zyw@rock-chips.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
On Wed, Mar 22, 2017 at 09:54:49AM +0800, Chris Zhong wrote: > For RK3399, the grf clock should be controlled by dw-mipi-dsi driver, > add the description for this clock. > > Signed-off-by: Chris Zhong <zyw@rock-chips.com> > Reviewed-by: Sean Paul <seanpaul@chromium.org> > --- > > Changes in v4: > - remove "additional" > > Changes in v3: None > Changes in v2: None > > .../devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Acked-by: Rob Herring <robh@kernel.org> -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt index 188f6f7..1d722f5 100644 --- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt +++ b/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt @@ -10,7 +10,7 @@ Required properties: - interrupts: Represent the controller's interrupt to the CPU(s). - clocks, clock-names: Phandles to the controller's pll reference clock(ref) and APB clock(pclk). For RK3399, a phy config clock - (phy_cfg) is additional required. As described in [1]. + (phy_cfg) and a grf clock(grf) are required. As described in [1]. - rockchip,grf: this soc should set GRF regs to mux vopl/vopb. - ports: contain a port node with endpoint definitions as defined in [2]. For vopb,set the reg = <0> and set the reg = <1> for vopl.