From patchwork Tue Mar 21 17:57:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Aaron Sawdey X-Patchwork-Id: 741686 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vngXJ2yskz9s7R for ; Wed, 22 Mar 2017 04:58:07 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="guL+7f73"; dkim-atps=neutral DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:date:content-type:mime-version:message-id; q= dns; s=default; b=suZJlReHYTLXWcElaPQ6WC+wTaSI2kicpRm1or0j8kgomy p6Dm7VNjN7Q8FWZJ7ZUtikuLvFK+Xc0CJHi5Co2IjNC3bi+qRKsg9KvbQL3QIptq oI/xnz2Z8WS2TFBvZa7d0RvJ8V2tTrCsmY8SWOtr8zL5ZH6SMRBaUDVYHIcHA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :subject:from:to:date:content-type:mime-version:message-id; s= default; bh=iku55S4upYmzhWwY/UXvfaQN+FU=; b=guL+7f73uF/cR636Cmsn NBtfHChxk48OG5u4KWsHpJ/hFY1w6QfgmUcX4YneqCvcz+huSV6zxvUcLPNZCGDO HO7IyTt7XYan+De30QZFoaHoSculiLGknQxRvkVDHOCfGRHF+KIvcReVMw46TPTq OEMG3ahXZNB+tqA9FylN+wA= Received: (qmail 42892 invoked by alias); 21 Mar 2017 17:57:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 42466 invoked by uid 89); 21 Mar 2017 17:57:57 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy=1336 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 21 Mar 2017 17:57:55 +0000 Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v2LHrikU105705 for ; Tue, 21 Mar 2017 13:57:55 -0400 Received: from e31.co.us.ibm.com (e31.co.us.ibm.com [32.97.110.149]) by mx0b-001b2d01.pphosted.com with ESMTP id 29b6aqr9f5-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 21 Mar 2017 13:57:54 -0400 Received: from localhost by e31.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 21 Mar 2017 11:57:50 -0600 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp07029.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v2LHvnkh15860056 for ; Tue, 21 Mar 2017 10:57:49 -0700 Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9631A6A047 for ; Tue, 21 Mar 2017 11:57:49 -0600 (MDT) Received: from ragesh3a (unknown [9.85.206.201]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTP id 437B76A045 for ; Tue, 21 Mar 2017 11:57:49 -0600 (MDT) Subject: [PATCH][PR target/80123][7 regression] new constraint wA to prevent r0 use in mtvsrdd From: Aaron Sawdey To: gcc-patches@gcc.gnu.org Date: Tue, 21 Mar 2017 12:57:43 -0500 Mime-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 17032117-8235-0000-0000-00000B2A344C X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006824; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000206; SDB=6.00836927; UDB=6.00411387; IPR=6.00614694; BA=6.00005227; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00014745; XFM=3.00000013; UTC=2017-03-21 17:57:52 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17032117-8236-0000-0000-00003A806CCA Message-Id: <1490119063.5885.12.camel@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-21_15:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703210153 X-IsSubscribed: yes Both the fails in 80123 are a situation where vsx_splat_ for V2DI generates rtl for a mtvsrdd but constraint wr doesn't prevent allocation of r0 for the input. So new constraint wA combines the attributes of wr and b -- it is BASE_REGS if 64-bit and NO_REGS otherwise. Currently doing bootstrap/regtest on 64-bit LE and BE, and also BE 32- bit. OK for trunk if everything passes? 2017-03-21  Aaron Sawdey   PR target/80123 * doc/md.texi (Constraints): Document wA constraint. * config/rs6000/constraints.md (wA): New. * config/rs6000/rs6000.c (rs6000_debug_reg_global): Add wA reg_class. (rs6000_init_hard_regno_mode_ok): Init wA constraint. * config/rs6000/rs6000.h (RS6000_CONSTRAINT_wA): New. * config/rs6000/vsx.md (vsx_splat_): Use wA constraint. Index: gcc/config/rs6000/constraints.md =================================================================== --- gcc/config/rs6000/constraints.md (revision 246295) +++ gcc/config/rs6000/constraints.md (working copy) @@ -133,6 +133,9 @@ (define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") +(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]" + "BASE_REGS if 64-bit instructions are enabled or NO_REGS.") + ;; wB needs ISA 2.07 VUPKHSW (define_constraint "wB" "Signed 5-bit constant integer that can be loaded into an altivec register." Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 246295) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -2468,6 +2468,7 @@ "wx reg_class = %s\n" "wy reg_class = %s\n" "wz reg_class = %s\n" + "wA reg_class = %s\n" "wH reg_class = %s\n" "wI reg_class = %s\n" "wJ reg_class = %s\n" @@ -2500,6 +2501,7 @@ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wy]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wz]], + reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wH]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wI]], reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wJ]], @@ -3210,7 +3212,10 @@ } if (TARGET_POWERPC64) - rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; + { + rs6000_constraints[RS6000_CONSTRAINT_wr] = GENERAL_REGS; + rs6000_constraints[RS6000_CONSTRAINT_wA] = BASE_REGS; + } if (TARGET_P8_VECTOR && TARGET_UPPER_REGS_SF) /* SFmode */ { Index: gcc/config/rs6000/rs6000.h =================================================================== --- gcc/config/rs6000/rs6000.h (revision 246295) +++ gcc/config/rs6000/rs6000.h (working copy) @@ -1612,6 +1612,7 @@ RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */ RS6000_CONSTRAINT_wy, /* VSX register for SF */ RS6000_CONSTRAINT_wz, /* FPR register for LFIWZX */ + RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */ RS6000_CONSTRAINT_wH, /* Altivec register for 32-bit integers. */ RS6000_CONSTRAINT_wI, /* VSX register for 32-bit integers. */ RS6000_CONSTRAINT_wJ, /* VSX register for 8/16-bit integers. */ Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (revision 246295) +++ gcc/config/rs6000/vsx.md (working copy) @@ -3072,7 +3072,7 @@ "=, ,we,") (vec_duplicate:VSX_D (match_operand: 1 "splat_input_operand" - ",Z, b, wr")))] + ",Z, b, wA")))] "VECTOR_MEM_VSX_P (mode)" "@ xxpermdi %x0,%x1,%x1,0 Index: gcc/doc/md.texi =================================================================== --- gcc/doc/md.texi (revision 246295) +++ gcc/doc/md.texi (working copy) @@ -3122,6 +3122,9 @@ @item wz Floating point register if the LFIWZX instruction is enabled or NO_REGS. +@item wA +Address base register if 64-bit instructions are enabled or NO_REGS. + @item wB Signed 5-bit constant integer that can be loaded into an altivec register.