From patchwork Mon Mar 20 16:14:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacopo Mondi X-Patchwork-Id: 741092 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vn2rR4Sjwz9s7B for ; Tue, 21 Mar 2017 04:24:55 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755025AbdCTRYP (ORCPT ); Mon, 20 Mar 2017 13:24:15 -0400 Received: from slow1-d.mail.gandi.net ([217.70.178.86]:58728 "EHLO slow1-d.mail.gandi.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753104AbdCTRYM (ORCPT ); Mon, 20 Mar 2017 13:24:12 -0400 Received: from relay4-d.mail.gandi.net (relay4-d.mail.gandi.net [217.70.183.196]) by slow1-d.mail.gandi.net (Postfix) with ESMTP id 17C23496430; Mon, 20 Mar 2017 17:16:21 +0100 (CET) Received: from w540.lan (unknown [IPv6:2001:b07:6442:1ac4:30ee:93b1:e300:81e]) (Authenticated sender: jacopo@jmondi.org) by relay4-d.mail.gandi.net (Postfix) with ESMTPSA id 554071722D3; Mon, 20 Mar 2017 17:15:09 +0100 (CET) From: Jacopo Mondi To: geert+renesas@glider.be, laurent.pinchart@ideasonboard.com, chris.brandt@renesas.com, linus.walleij@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, linux@armlinux.org.uk Cc: linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/7] dt-bindings: pinctrl: Add RZ/A1 bindings doc Date: Mon, 20 Mar 2017 17:14:46 +0100 Message-Id: <1490026491-21742-3-git-send-email-jacopo+renesas@jmondi.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1490026491-21742-1-git-send-email-jacopo+renesas@jmondi.org> References: <1490026491-21742-1-git-send-email-jacopo+renesas@jmondi.org> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add device tree bindings documentation for Renesas RZ/A1 gpio and pin controller. Signed-off-by: Jacopo Mondi --- .../bindings/pinctrl/renesas,rza1-pinctrl.txt | 144 +++++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt new file mode 100644 index 0000000..0474860 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt @@ -0,0 +1,144 @@ +Renesas RZ/A1 combined Pin and GPIO controller + +Renesas SoCs of RZ/A1 family feature a combined Pin and GPIO controller +hardware controller, named "Ports" in the hardware reference manual. +Pin multiplexing and GPIO configuration is performed on a per-pin basis +writing configuration values to per-port register sets. +Each "port" features up to 16 pins, each of them configurable for GPIO +function (port mode) or in alternate function mode. +Up to 8 different alternate function modes exist for each single pin. + +Pin controller node +------------------- + +Required properties: + - compatible + this shall be "renesas,r7s72100-ports". + + - #pinctrl-cells + as defined by pinctrl-bindings.txt, this is the number + of cells (in addition to pin index) required to configure a single pin. + Shall be set to 1. + + - reg + address base and length of the memory area where pin controller + hardware is mapped to. + +Example: +Pin controller node for RZ/A1H SoC (r7s72100) + +pinctrl: pinctrl@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + #pinctrl-cells = <1>; + + reg = <0xfcfe3000 0x4248>; +}; + +Sub-nodes +--------- + +The child nodes of the pin controller node describe a pin multiplexing +function or a gpio controller alternatively. + +- Pin multiplexing sub-nodes: + A pin multiplexing sub-node describes how to configure a set of + (or a single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations groups. + + Required properties: + - renesas,pins + describes an array of pin multiplexing configurations. + When a pin has to be configured in alternate function mode, use this + property to identify the pin by its global index, and provide its + alternate function configuration description along with it. + When multiple pins are required to be configured as part of the same + alternate function (odds are single-pin alternate functions exist) they + shall be specified as members of the same argument list of a single + "renesas-pins" property. + Helper macros to ease calculating the pin index from its position + (port where it sits on and pin offset), and alternate function + configuration options are provided in pin controller header file at: + include/dt-bindings/pinctrl/r7s72100-pinctrl.h + + Example: + A serial communication interface with a TX output pin and a RX input pin. + + &pinctrl { + scif2_pins: serial2 { + renesas,pins = , + ; + }; + } + + Pin #0 on port #3 is configured in alternate function #6. + Pin #2 on port #3 is configured in alternate function #4. + + Example 2: + I2c master: both SDA and SCL pins need bi-directional operations + + &pinctrl { + i2c2_pins: i2c2 { + renesas,pins = , + ; + }; + } + + Pin #4 on port #1 is configured in alternate function #1. + Pin #5 on port #1 is configured in alternate function #1. + Both need to work in bi-directional mode. + + Example 3: + Multi-function timer input and output compare pins. + The hardware manual prescribes this pins to have input/output direction + specified by software. Configure TIOC0A as input and TIOC0B as output. + + &pinctrl { + tioc0_pins: tioc0 { + renesas,pins = , + ; + }; + } + + Pin #0 on port #4 is configured in alternate function #2 with IO direction + specified by software as input. + Pin #1 on port #4 is configured in alternate function #1 with IO direction + specified by software as output. + +- GPIO controller sub-nodes: + Each port of r7s72100 pin controller hardware is itself a gpio controller. + Different SoCs have different number of available pins per port, but + generally speaking, each of them can be configured in GPIO ("port") mode + on this hardware. + Describe gpio-controllers using sub-nodes with the following properties. + + Required properties: + - gpio-controller + empty property as defined by gpio bindings documentation. + - #gpio-cells + number of cells required to identify and configure a GPIO. + Shall be 2. + - gpio-ranges + Describes a gpio controller specifying its specific pin base, the pin + base in the global pin numbering space, and the number of controlled + pins, as defined by gpio bindings documentation. Refer to this file + for a more detailed description. + + Example: + A gpio controller node, controlling 16 pins indexed from 0. + The gpio controller base in the global pin indexing space is pin 48, thus + pins [0 - 15] on this controller map to pins [48 - 63] in the global pin + indexing space. + + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + A device node willing to use pins controlled by this gpio controller, shall + refer to it as follows: + + led1 { + gpios = <&port3 10 GPIO_ACTIVE_LOW>; + };