From patchwork Sun Mar 19 18:59:34 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 740739 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vmT8t1gqBz9s3w for ; Mon, 20 Mar 2017 06:07:10 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.b="OkR1FpsJ"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id ED498C21C93; Sun, 19 Mar 2017 19:04:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4078DC21C5A; Sun, 19 Mar 2017 19:02:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 67C01C21C49; Sun, 19 Mar 2017 19:00:24 +0000 (UTC) Received: from mail-oi0-f46.google.com (mail-oi0-f46.google.com [209.85.218.46]) by lists.denx.de (Postfix) with ESMTPS id 03FF6C21C5E for ; Sun, 19 Mar 2017 19:00:20 +0000 (UTC) Received: by mail-oi0-f46.google.com with SMTP id a94so14122927oic.2 for ; Sun, 19 Mar 2017 12:00:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=U1cqosPDi90nleQXBZ5JNWe47P5XfLcVG12AiOwDMl8=; b=OkR1FpsJwcjuQhtTU0DT1uIn1nfArJWk1/lTV0M6zwLvJt0H/NVl3nNCQHbxbZ+v24 XrKzk774aETVhkzqofSz9BrvwJb+qXMCPKgn1B7LQz0tJikKixzHPgt7XpFXGuLmNS7v xkciAFmOXmlAnCmPnFxygIxmoAC/WmHybH2m+Rt3AIGMnxU6OVNzPLo/UGDr9fZ/FYYg SobTmzf2BN9TEYfIFIeXyvi+jji/+5/pvTLDceN/8FINMTzdQeMWmQk0Np/fKJ9RTDO/ GTg+eulyamuhcdTzx3PUqkBecHK74vMlF2cE2L0wG0WiBzbOpTIf1p9cqsaZjWzLyuZH ltHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=U1cqosPDi90nleQXBZ5JNWe47P5XfLcVG12AiOwDMl8=; b=rcTumUUfr4WlNyR189HqkZIoThpU9aJQl2MdDDXDFwt2N6Ep4YLLQozUrKW2+EpBpG rSzu1tyydnb0Af5pRpJcx6E7r5fGcNnL0zNJBzsTG6vbKXXjafPkpK0sAvAcF74nFTOp BFw1oREYlzr1lYMwbozDnGP3VbMUmutV6AG3g35pC6NxjR6HNNtrADzPduYoQXeI5tuh o7Iidv88jmlBgEScY8wfU7+Bl07q8LIZklSz+9FWoSc33ViHusyL9VSruVgBRxi8H6n4 BqSMLmT2n4YnpJlxPANkt0ckVpECYBEssa3TiZvDg73oTgCzACHPn+7KjYH70nFbomFz VC6Q== X-Gm-Message-State: AFeK/H3Y4ZXLlVRqtF0ZeNRuitO+dvcTUFfjkEZKVPkYBzPW099bGBv/qSw/58epY3J/tW0u X-Received: by 10.202.55.197 with SMTP id e188mr14559539oia.12.1489950018763; Sun, 19 Mar 2017 12:00:18 -0700 (PDT) Received: from kaki.bld.corp.google.com ([2620:0:1005:11:4b6:487f:844b:c8b6]) by smtp.gmail.com with ESMTPSA id v16sm6561702otf.8.2017.03.19.12.00.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 19 Mar 2017 12:00:18 -0700 (PDT) Received: by kaki.bld.corp.google.com (Postfix, from userid 121222) id 8CF1F40083; Sun, 19 Mar 2017 13:00:17 -0600 (MDT) From: Simon Glass To: U-Boot Mailing List Date: Sun, 19 Mar 2017 12:59:34 -0600 Message-Id: <20170319185935.20950-16-sjg@chromium.org> X-Mailer: git-send-email 2.12.0.367.g23dc2f6d3c-goog In-Reply-To: <20170319185935.20950-1-sjg@chromium.org> References: <20170319185935.20950-1-sjg@chromium.org> Cc: Tom Rini Subject: [U-Boot] [PATCH 15/16] dm: x86: board: ivybridge: Remove old board init code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Remove the legacy board init code since it is no-longer used. Signed-off-by: Simon Glass --- arch/x86/cpu/ivybridge/cpu.c | 16 +--------------- arch/x86/cpu/ivybridge/sdram.c | 7 ------- arch/x86/cpu/ivybridge/sdram_nop.c | 7 ------- arch/x86/lib/spl.c | 13 ------------- board/google/chromebook_link/link.c | 7 ------- board/google/chromebox_panther/panther.c | 7 ------- 6 files changed, 1 insertion(+), 56 deletions(-) diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 96e69ef792..e7e6c3168a 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -84,13 +84,6 @@ static int do_arch_cpu_init_dm(void) return 0; } -#ifndef CONFIG_BOARD_ENABLE -int arch_cpu_init_dm(void) -{ - return do_arch_cpu_init_dm(); -} -#endif - #define PCH_EHCI0_TEMP_BAR0 0xe8000000 #define PCH_EHCI1_TEMP_BAR0 0xe8000400 #define PCH_XHCI_TEMP_BAR0 0xe8001000 @@ -133,7 +126,7 @@ static void enable_usb_bar(struct udevice *bus) pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32); } -static int ivybridge_checkcpu(void) +int ivybridge_checkcpu(void) { enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE; struct udevice *dev, *lpc; @@ -192,13 +185,6 @@ static int ivybridge_checkcpu(void) return 0; } -#ifndef CONFIG_BOARD_ENABLE -int print_cpuinfo(void) -{ - return ivybridge_checkcpu(); -} -#endif - void board_debug_uart_init(void) { /* This enables the debug UART */ diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index 2484ed4859..eb4d04f8da 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -559,10 +559,3 @@ int ivybridge_dram_init(void) return 0; } - -#ifndef CONFIG_BOARD_ENABLE -int dram_init(void) -{ - return ivybridge_dram_init(); -} -#endif diff --git a/arch/x86/cpu/ivybridge/sdram_nop.c b/arch/x86/cpu/ivybridge/sdram_nop.c index 641d099bbf..6bf5366410 100644 --- a/arch/x86/cpu/ivybridge/sdram_nop.c +++ b/arch/x86/cpu/ivybridge/sdram_nop.c @@ -18,13 +18,6 @@ int nop_dram_init(void) return 0; } -#ifndef CONFIG_BOARD_ENABLE -int dram_init(void) -{ - return nop_dram_init(); -} -#endif - static int cpu_x86_nop_phase(struct udevice *dev, enum board_phase_t phase) { switch (phase) { diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c index a4c1a3ac35..0d40a6f41e 100644 --- a/arch/x86/lib/spl.c +++ b/arch/x86/lib/spl.c @@ -48,7 +48,6 @@ static int x86_spl_init(void) return ret; } preloader_console_init(); -#ifdef CONFIG_BOARD_ENABLE ret = board_walk_phase(BOARD_F_CHECKCPU); if (ret) { debug("%s: BOARD_F_CHECKCPU failed\n", __func__); @@ -59,18 +58,6 @@ static int x86_spl_init(void) debug("%s: BOARD_F_DRAM_INIT failed\n", __func__); return ret; } -#else - ret = print_cpuinfo(); - if (ret) { - debug("%s: print_cpuinfo() failed\n", __func__); - return ret; - } - ret = dram_init(); - if (ret) { - debug("%s: dram_init() failed\n", __func__); - return ret; - } -#endif memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */ diff --git a/board/google/chromebook_link/link.c b/board/google/chromebook_link/link.c index 99b1c91edc..64e7c1a08d 100644 --- a/board/google/chromebook_link/link.c +++ b/board/google/chromebook_link/link.c @@ -16,10 +16,3 @@ int arch_early_init_r(void) { return 0; } - -#ifndef CONFIG_BOARD_ENABLE -int board_early_init_f(void) -{ - return 0; -} -#endif diff --git a/board/google/chromebox_panther/panther.c b/board/google/chromebox_panther/panther.c index 151cdd719d..ed60e44264 100644 --- a/board/google/chromebox_panther/panther.c +++ b/board/google/chromebox_panther/panther.c @@ -11,10 +11,3 @@ int arch_early_init_r(void) { return 0; } - -#ifndef CONFIG_BOARD_ENABLE -int board_early_init_f(void) -{ - return 0; -} -#endif