From patchwork Fri Mar 17 17:44:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ralph Sennhauser X-Patchwork-Id: 740410 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vlCQC5YFWz9ryZ for ; Sat, 18 Mar 2017 04:44:19 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="hdRO4zoe"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751087AbdCQRoT (ORCPT ); Fri, 17 Mar 2017 13:44:19 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:33945 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751133AbdCQRoR (ORCPT ); Fri, 17 Mar 2017 13:44:17 -0400 Received: by mail-wm0-f65.google.com with SMTP id u132so4404200wmg.1; Fri, 17 Mar 2017 10:44:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=rXkKst3/knlFatY7LACpCzfkxZH+4Ts4dRMwdX/XHUA=; b=hdRO4zoeBnbthVC6PiEBl55tWuoxQUtqX1asplBBg2/be+BwPa3yJ09gu25eSJNkJh 39uV0kTQPruZTKujj/MmHlls4rM6Q+yGsQLiGnjHk6VqY2e3Sg/zLeeZpaC3WwIGDySr xquXJooTR2DIgp9jJ86Uqxj9bqeOpTSW2rKJiowZMo/U/3FDrIZpYMW4tuB4bKclhDCp 24vl4hdw6mWt9QGDSqIF2IlHzEKr2mBuL2eAp4QiBEPc4gTn+qMBJPXGcRc5pkHiJP+P hvJStArEci+FgB4Xrj0QBIiBheWtxP03aK88CJWmTsA+uESJvxA4I5PZjwJ3LjVcF7fM P8kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=rXkKst3/knlFatY7LACpCzfkxZH+4Ts4dRMwdX/XHUA=; b=UMUg+dmEzv7Hj8tORFxDD+oxA+MExZi1aVZQReDJMfD7L+bXeKjMNRDkc7B85VEeT3 bKVrISlMSN0pvqdBw/prhAVV4Ud+wOmxOPyro+q1Wa9nMEHKisN+94m3EnjaQFhPNTpK +I92vfwbSiZZBHE5f6ayIPP6mXxjhBiwWgxSC72EekBUqguB2KvOzNWwm1/5yBywOLQI xJHuA6US+ZbhYPYnuPjsfDZC9MKp+ImjrEjMpoKylRPxjHwhGM2lBliDoxgrXiUKUy7D EZW+wgCyi7AfAa2sRk3ow6QrFsMefXrpoyUSsDZhZGjq9qFNSjDb6ga0lHH/vrL9AkMu 1Tjw== X-Gm-Message-State: AFeK/H2PgrzdR4muW0RgwAONASzTRG5q/Yc+6ZJOQmKe+Av/Fn0sUtAvqwG7z0TCA32b2Q== X-Received: by 10.28.96.65 with SMTP id u62mr3652462wmb.88.1489772655104; Fri, 17 Mar 2017 10:44:15 -0700 (PDT) Received: from localhost.lan ([37.209.189.139]) by smtp.googlemail.com with ESMTPSA id d42sm10741783wrd.37.2017.03.17.10.44.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Mar 2017 10:44:13 -0700 (PDT) From: Ralph Sennhauser To: Linus Walleij Cc: Ralph Sennhauser , Alexandre Courbot , linux-gpio@vger.kernel.org (open list:GPIO SUBSYSTEM), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/1] gpio: mvebu: use BIT macro instead of bit shifting Date: Fri, 17 Mar 2017 18:44:06 +0100 Message-Id: <20170317174406.13431-1-ralph.sennhauser@gmail.com> X-Mailer: git-send-email 2.10.2 Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Use the BIT macro instead of explicitly shifting bits for some added clarity. Signed-off-by: Ralph Sennhauser --- Hi Linus, To use the BIT macro for the pwm-fan addition it would be nice to have the rest converted before hand. This patch takes care of that. Ralph drivers/gpio/gpio-mvebu.c | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c index 029f43c..fae4db6 100644 --- a/drivers/gpio/gpio-mvebu.c +++ b/drivers/gpio/gpio-mvebu.c @@ -45,6 +45,7 @@ #include #include #include +#include /* * GPIO unit register offsets. @@ -191,9 +192,9 @@ static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) spin_lock_irqsave(&mvchip->lock, flags); u = readl_relaxed(mvebu_gpioreg_out(mvchip)); if (value) - u |= 1 << pin; + u |= BIT(pin); else - u &= ~(1 << pin); + u &= ~BIT(pin); writel_relaxed(u, mvebu_gpioreg_out(mvchip)); spin_unlock_irqrestore(&mvchip->lock, flags); } @@ -203,7 +204,7 @@ static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); u32 u; - if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { + if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin)) { u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); } else { @@ -223,9 +224,9 @@ static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, spin_lock_irqsave(&mvchip->lock, flags); u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); if (value) - u |= 1 << pin; + u |= BIT(pin); else - u &= ~(1 << pin); + u &= ~BIT(pin); writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); spin_unlock_irqrestore(&mvchip->lock, flags); } @@ -247,7 +248,7 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) spin_lock_irqsave(&mvchip->lock, flags); u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); - u |= 1 << pin; + u |= BIT(pin); writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); spin_unlock_irqrestore(&mvchip->lock, flags); @@ -275,7 +276,7 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, spin_lock_irqsave(&mvchip->lock, flags); u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); - u &= ~(1 << pin); + u &= ~BIT(pin); writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); spin_unlock_irqrestore(&mvchip->lock, flags); @@ -392,7 +393,7 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) pin = d->hwirq; - u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); + u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin); if (!u) return -EINVAL; @@ -412,13 +413,13 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_LEVEL_HIGH: u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); - u &= ~(1 << pin); + u &= ~BIT(pin); writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); break; case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_LEVEL_LOW: u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); - u |= 1 << pin; + u |= BIT(pin); writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); break; case IRQ_TYPE_EDGE_BOTH: { @@ -431,10 +432,10 @@ static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) * set initial polarity based on current input level */ u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); - if (v & (1 << pin)) - u |= 1 << pin; /* falling */ + if (v & BIT(pin)) + u |= BIT(pin); /* falling */ else - u &= ~(1 << pin); /* rising */ + u &= ~BIT(pin); /* rising */ writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); break; } @@ -464,7 +465,7 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc) irq = irq_find_mapping(mvchip->domain, i); - if (!(cause & (1 << i))) + if (!(cause & BIT(i))) continue; type = irq_get_trigger_type(irq); @@ -473,7 +474,7 @@ static void mvebu_gpio_irq_handler(struct irq_desc *desc) u32 polarity; polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); - polarity ^= 1 << i; + polarity ^= BIT(i); writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); } @@ -510,7 +511,7 @@ static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) if (!label) continue; - msk = 1 << i; + msk = BIT(i); is_out = !(io_conf & msk); seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label);