From patchwork Fri Mar 17 09:58:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: M'boumba Cedric Madianga X-Patchwork-Id: 740216 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vl17v22gYz9s0Z for ; Fri, 17 Mar 2017 21:01:15 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="sjCn9UvG"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751355AbdCQKAg (ORCPT ); Fri, 17 Mar 2017 06:00:36 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:32946 "EHLO mail-wm0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751463AbdCQJ7Y (ORCPT ); Fri, 17 Mar 2017 05:59:24 -0400 Received: by mail-wm0-f65.google.com with SMTP id n11so2383917wma.0; Fri, 17 Mar 2017 02:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=hOQOCuuky/Nf+OxddbGe1T9ANGJ4JpI4z+hl+kHl4bs=; b=sjCn9UvGbpSv8Wei1BdgA5QIcn2FLcJSOBzGVrBx9iKbMTTHym6zi1xgOQS1VCNHVw SWiEoSIsosbb0cFgmIhbo5eHCv1U+/Fkgmy3adz3G9+4gn2DuAf43ydo3a/GOGPhnxiB PuBz4WaF/si+rm8I4FIFCVyGajfR3WK9jvy7xfv26taXDEAsQdtIq+oRCk6bDlHDMTHH VoQvzO7vlP7l2z6Tav/yLxH5h8u6AnWptK+OAjgK3DyMfksbaT/hbsJ+d5V2LOZLXxoo 55B3dJKYY4E0nTDX3PQRWWBwhGmRw9KvtMouR+owuad0S8EMz1B48oV4RyEf12JpfIMe vESg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=hOQOCuuky/Nf+OxddbGe1T9ANGJ4JpI4z+hl+kHl4bs=; b=i88bm7OEzzaYSXvYTUJpZJAEMLt5zwk8Zo5acNgOiWxgli7awLlZgL9+XKLr0UqUJc ptqh7/sWTvAxqiv5TOCt78qnNssj2Xh0XwAMfjIii0IvN2T3cvGjyfNCsviEHIElnxiI 33xNFyACJQIusODx647cfpADsWOHYt1oG+luwqe7Jwp1E3z2h8y0r+XqwV/svf4YOC2T I4uHLZex2a/MP40xTKoAjEkwMvONoUzmVhVORQysMEzPjUD6TC8gxYoe3rHxQINCvdfi 14ed2QPB+z3RidHWo2IWDe4S9UuHdSE2X1jRht9ClDN/wreAUpZgppm4CXwotPorCRtG pnGw== X-Gm-Message-State: AFeK/H1dIXDc8MvBbWioQIIj7t/MhZi7XgFXlJXIXEmgtRi2awm089sFO6xiUZ4C8QCA8A== X-Received: by 10.28.136.81 with SMTP id k78mr1947406wmd.36.1489744756601; Fri, 17 Mar 2017 02:59:16 -0700 (PDT) Received: from lmenx29w.st.com. ([37.165.103.73]) by smtp.gmail.com with ESMTPSA id o52sm9356959wrb.51.2017.03.17.02.59.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 17 Mar 2017 02:59:15 -0700 (PDT) From: M'boumba Cedric Madianga To: wsa@the-dreams.de, robh+dt@kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@st.com, linus.walleij@linaro.org, pierre-yves.mordret@st.com, linux@armlinux.org.uk, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: M'boumba Cedric Madianga Subject: [PATCH 4/5] ARM: dts: stm32: Add I2C1 support for STM32F746 SoC Date: Fri, 17 Mar 2017 10:58:57 +0100 Message-Id: <1489744738-21632-5-git-send-email-cedric.madianga@gmail.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1489744738-21632-1-git-send-email-cedric.madianga@gmail.com> References: <1489744738-21632-1-git-send-email-cedric.madianga@gmail.com> Sender: linux-i2c-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org This patch adds I2C1 support for STM32F746 SoC. Signed-off-by: M'boumba Cedric Madianga --- arch/arm/boot/dts/stm32f746.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index f321ffe..89d3897 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -287,6 +287,29 @@ bias-disable; }; }; + + i2c1_pins_b: i2c1@0 { + pins { + pinmux = , + ; + bias-disable; + drive-open-drain; + slew-rate = <3>; + }; + }; + }; + + i2c1: i2c@40005400 { + compatible = "st,stm32f7-i2c"; + reg = <0x40005400 0x400>; + interrupts = <31>, + <32>; + resets = <&rcc 149>; + clocks = <&rcc 0 405>; + st,i2c-timing = <0x40202537>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; rcc: rcc@40023800 {