From patchwork Fri Mar 17 09:25:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 740202 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vl0X55k1lz9ryj for ; Fri, 17 Mar 2017 20:33:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751143AbdCQJdl (ORCPT ); Fri, 17 Mar 2017 05:33:41 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:12377 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751122AbdCQJdj (ORCPT ); Fri, 17 Mar 2017 05:33:39 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 17 Mar 2017 02:33:23 -0700 Received: from HQMAIL103.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 17 Mar 2017 02:27:38 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 17 Mar 2017 02:27:38 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Fri, 17 Mar 2017 09:25:54 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Fri, 17 Mar 2017 09:25:55 +0000 Received: from goldfinger.nvidia.com (Not Verified[10.21.132.151]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Fri, 17 Mar 2017 02:25:54 -0700 From: Jon Hunter To: Adrian Hunter , Ulf Hansson , Thierry Reding , Ritesh Harjani CC: , , , Jon Hunter Subject: [PATCH V2 2/2] mmc: tegra: Fix setting of Tegra SDHCI module clock Date: Fri, 17 Mar 2017 09:25:32 +0000 Message-ID: <1489742732-7722-2-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489742732-7722-1-git-send-email-jonathanh@nvidia.com> References: <1489742732-7722-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Commit a8e326a911d3 ("mmc: tegra: implement module external clock change") implemented the SDHCI 'set_clock' handler for Tegra in order to change the module clock for the Tegra SDHCI controller by using the common clock framework API clk_set_rate(). The problem is the clk_set_rate() may sleep and the 'set_clock' handler is always called from within the context of a spinlock. Hence, occasionally, 'scheduling while atomic' errors are seen. Fix this by moving the setting of the module clock to the new 'set_parent_clock' handler which is not called from within the context of a spinlock. Fixes: a8e326a911d3 ("mmc: tegra: implement module external clock change") Signed-off-by: Jon Hunter Reviewed-by: Thierry Reding --- Changes since V1: - None drivers/mmc/host/sdhci-tegra.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 20b6ff5b4af1..048f84e615d3 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -217,18 +217,25 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) sdhci_writel(host,val, SDHCI_TEGRA_AUTO_CAL_CONFIG); } -static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +static void tegra_sdhci_set_parent_clock(struct sdhci_host *host, + unsigned int clock) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); unsigned long host_clk; if (!clock) - return sdhci_set_clock(host, clock); + return; host_clk = tegra_host->ddr_signaling ? clock * 2 : clock; - clk_set_rate(pltfm_host->clk, host_clk); + WARN_ON(clk_set_rate(pltfm_host->clk, host_clk)); host->max_clk = clk_get_rate(pltfm_host->clk); +} + +static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); sdhci_set_clock(host, clock); @@ -320,6 +327,7 @@ static const struct sdhci_ops tegra_sdhci_ops = { .read_w = tegra_sdhci_readw, .write_l = tegra_sdhci_writel, .set_clock = tegra_sdhci_set_clock, + .set_parent_clock = tegra_sdhci_set_parent_clock, .set_bus_width = tegra_sdhci_set_bus_width, .reset = tegra_sdhci_reset, .platform_execute_tuning = tegra_sdhci_execute_tuning, @@ -368,6 +376,7 @@ static const struct sdhci_ops tegra114_sdhci_ops = { .write_w = tegra_sdhci_writew, .write_l = tegra_sdhci_writel, .set_clock = tegra_sdhci_set_clock, + .set_parent_clock = tegra_sdhci_set_parent_clock, .set_bus_width = tegra_sdhci_set_bus_width, .reset = tegra_sdhci_reset, .platform_execute_tuning = tegra_sdhci_execute_tuning,