From patchwork Fri Mar 17 07:24:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shawn Lin X-Patchwork-Id: 740188 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vkyP46WMWz9ryT for ; Fri, 17 Mar 2017 18:57:28 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751018AbdCQH52 (ORCPT ); Fri, 17 Mar 2017 03:57:28 -0400 Received: from ca-mx01.263.net ([50.18.194.75]:19692 "EHLO smtphy.263.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750926AbdCQH51 (ORCPT ); Fri, 17 Mar 2017 03:57:27 -0400 X-Greylist: delayed 970 seconds by postgrey-1.27 at vger.kernel.org; Fri, 17 Mar 2017 03:57:27 EDT Received: from transport.263xmail.com (unknown [38.83.106.156]) by smtphy.263.net (Postfix) with ESMTPS id 42D8FA01D8 for ; Fri, 17 Mar 2017 15:41:15 +0800 (CST) Received: from lucky1.263xmail.com (unknown [192.168.165.164]) by transportlucky.263xmail.com (Postfix) with ESMTP id 8A3CD4389 for ; Fri, 17 Mar 2017 15:41:10 +0800 (CST) Received: from shawn.lin?rock-chips.com (unknown [192.168.167.177]) by lucky1.263xmail.com (Postfix) with ESMTP id C94901EF4CB; Fri, 17 Mar 2017 15:28:27 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 79BB3490; Fri, 17 Mar 2017 15:28:23 +0800 (CST) X-RL-SENDER: shawn.lin@rock-chips.com X-FST-TO: bhelgaas@google.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: shawn.lin@rock-chips.com X-UNIQUE-TAG: <573207852c9867d114e79f7748bf7297> X-ATTACHMENT-NUM: 0 X-SENDER: lintao@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 5371S3Q9EH; Fri, 17 Mar 2017 15:28:24 +0800 (CST) From: Shawn Lin To: Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-rockchip@lists.infradead.org, Wenrui Li , Brian Norris , Jeffy Chen , Shawn Lin Subject: [PATCH] PCI: rockchip: Mark SLC bit as well as CCC bit for RC Date: Fri, 17 Mar 2017 15:24:53 +0800 Message-Id: <1489735493-148838-1-git-send-email-shawn.lin@rock-chips.com> X-Mailer: git-send-email 1.9.1 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org lspci traces CCC to see if the end-2-end supports common clock, so the current code should work as we mark the CCC bit of RC. However, ASPM code actually check SLC bit of RC and try to compare it with the downstream components' SLC instead. So when enabling ASPM, CCC will be cleared after failing to match SLC with the corresponding bit of downstream components. On one hand, from the code of pcie_aspm_configure_common_clock, we could find that what we actually need to set is SLC. On the other hand, we should also guarantee that CCC should be marked w/o supporting ASPM. This patch fixes this issue. Cc: Brian Norris Cc: jeffy.chen Signed-off-by: Shawn Lin Reviewed-by: Brian Norris Tested-by: Brian Norris --- drivers/pci/host/pcie-rockchip.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c index 26ddd35..7cd4d5c 100644 --- a/drivers/pci/host/pcie-rockchip.c +++ b/drivers/pci/host/pcie-rockchip.c @@ -596,7 +596,7 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) /* Set RC's clock architecture as common clock */ status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS); - status |= PCI_EXP_LNKCTL_CCC; + status |= (PCI_EXP_LNKCTL_CCC | PCI_EXP_LNKSTA_SLC << 16); rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS); /* Enable Gen1 training */