From patchwork Thu Mar 16 14:26:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 739858 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3vkW9V0pnxz9rvt for ; Fri, 17 Mar 2017 01:30:54 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="EEuIYQ9o"; dkim-atps=neutral Received: by lists.denx.de (Postfix, from userid 105) id A22E8C21C72; Thu, 16 Mar 2017 14:25:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 13B36C21C48; Thu, 16 Mar 2017 14:23:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5BCA2C21C50; Thu, 16 Mar 2017 14:22:39 +0000 (UTC) Received: from mail-pg0-f67.google.com (mail-pg0-f67.google.com [74.125.83.67]) by lists.denx.de (Postfix) with ESMTPS id C441AC21C70 for ; Thu, 16 Mar 2017 14:22:35 +0000 (UTC) Received: by mail-pg0-f67.google.com with SMTP id b5so6290961pgg.1 for ; Thu, 16 Mar 2017 07:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=IEuOGe1xgnrmJpGI2QL8CCP2J1MFzy+7PWpNmVUXZRU=; b=EEuIYQ9ooSPEpr9l0n2IJaN19FNQEfaZsLUwyQFVkezgiCsZs70iKqhaUwJs/d1fSo zhDmHbslQY4Klt05aT9oAnbDYv2Me1mzy8+au1lsVHKHxHK3/Ev3DsXLz7/vg5OIDDza J7nKd7ybptVqS8nLav7ZzqM8JfW6BSiRKCQ09bxzNaXsr/gSg62M8QREslps9sp873jj V2baU23NZqr/Ev1oo3acbzzlEVUUQc9l7qsO3ZKVnhq4qqAjIpzH5X1EC3RZy1p2mILL FRT5ZlgTG7qKBxZgap9SpW1M0Pdd+83ksT0tmT5N/iTCgoMobw1oslx68XuJIBPBMngA wYhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=IEuOGe1xgnrmJpGI2QL8CCP2J1MFzy+7PWpNmVUXZRU=; b=NsTfCoqvDTg6sH5yiXUNDHIkD0UwA6C4gIagifR4prVC1emzgBCiXL8PaCa51vOdFH mYmxT6o1rhf0VzpveC96IddZHfoDfrH1mfLQqzt0RCTFqUDbciRf0XdeVxUBx8OyE2cK 4SVFpTmXSy6BEKtHpQsk7RK7RjnnhWXEQV6qxP8hL+mSSrK1UdbgmFqy8yXVJA9iOKvY smN1HNkdePriDip9rzvzeJP7yRZUgXUKf3Z933GDP/EI/Wt0COgSXeem16dce+WlSsNp yqRTm8aIQPykHskqT4Du1X+Axrkcjc6rmCbeFG929Ula1V9dVmjGYNrbKceyTITqD+3r W4eA== X-Gm-Message-State: AFeK/H3b7Z9x3ZgWquip3HYtbpIEufyM0z2xOK5KZ1SguPBzgygii6fapvQD3DyBwmQXZQ== X-Received: by 10.98.58.7 with SMTP id h7mr10824568pfa.234.1489674154370; Thu, 16 Mar 2017 07:22:34 -0700 (PDT) Received: from ala-d2121-lx1.wrs.com (unknown-157-139.windriver.com. [147.11.157.139]) by smtp.gmail.com with ESMTPSA id c64sm11039959pfa.45.2017.03.16.07.22.33 (version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Mar 2017 07:22:33 -0700 (PDT) From: Bin Meng To: Simon Glass , Stefan Roese , U-Boot Mailing List Date: Thu, 16 Mar 2017 07:26:39 -0700 Message-Id: <1489674408-17498-14-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1489674408-17498-1-git-send-email-bmeng.cn@gmail.com> References: <1489674408-17498-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 13/22] x86: fsp: Save stack address to CMOS for next S3 boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" At the end of pre-relocation phase, save the new stack address to CMOS and use it as the stack on next S3 boot for fsp_init() continuation function. Signed-off-by: Bin Meng Reviewed-by: Simon Glass --- arch/x86/cpu/cpu.c | 8 ++++++++ arch/x86/include/asm/cmos_layout.h | 31 +++++++++++++++++++++++++++++++ arch/x86/include/asm/u-boot-x86.h | 1 + arch/x86/lib/fsp/fsp_common.c | 30 +++++++++++++++++++++++++++++- 4 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/cmos_layout.h diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index afc8645..9e2aee2 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -278,6 +278,14 @@ int reserve_arch(void) high_table_reserve(); #endif +#if defined(CONFIG_HAVE_ACPI_RESUME) && defined(CONFIG_HAVE_FSP) + /* + * Save stack address to CMOS so that at next S3 boot, + * we can use it as the stack address for fsp_contiue() + */ + fsp_save_s3_stack(); +#endif + return 0; } #endif diff --git a/arch/x86/include/asm/cmos_layout.h b/arch/x86/include/asm/cmos_layout.h new file mode 100644 index 0000000..0a0a51e --- /dev/null +++ b/arch/x86/include/asm/cmos_layout.h @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2017, Bin Meng + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CMOS_LAYOUT_H +#define __CMOS_LAYOUT_H + +/* + * The RTC internal registers and RAM is organized as two banks of 128 bytes + * each, called the standard and extended banks. The first 14 bytes of the + * standard bank contain the RTC time and date information along with four + * registers, A - D, that are used for configuration of the RTC. The extended + * bank contains a full 128 bytes of battery backed SRAM. + * + * For simplicity in U-Boot we only support CMOS in the standard bank, and + * its base address starts from offset 0x10, which leaves us 112 bytes space. + */ +#define CMOS_BASE 0x10 + +/* + * The file records all offsets off CMOS_BASE that is currently used by + * U-Boot for various reasons. It is put in such a unified place in order + * to be consistent across platforms. + */ + +/* stack address for S3 boot in a FSP configuration, 4 bytes */ +#define CMOS_FSP_STACK_ADDR CMOS_BASE + +#endif /* __CMOS_LAYOUT_H */ diff --git a/arch/x86/include/asm/u-boot-x86.h b/arch/x86/include/asm/u-boot-x86.h index 4f901f9..024aaf4 100644 --- a/arch/x86/include/asm/u-boot-x86.h +++ b/arch/x86/include/asm/u-boot-x86.h @@ -56,6 +56,7 @@ u32 isa_map_rom(u32 bus_addr, int size); int video_bios_init(void); /* arch/x86/lib/fsp/... */ +int fsp_save_s3_stack(void); int x86_fsp_init(void); void board_init_f_r_trampoline(ulong) __attribute__ ((noreturn)); diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 2b33fba..df73a2a 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -5,8 +5,12 @@ */ #include +#include #include +#include #include +#include +#include #include #include #include @@ -71,9 +75,32 @@ static __maybe_unused void *fsp_prepare_mrc_cache(void) return cache->data; } +#ifdef CONFIG_HAVE_ACPI_RESUME +int fsp_save_s3_stack(void) +{ + struct udevice *dev; + int ret; + + if (gd->arch.prev_sleep_state == ACPI_S3) + return 0; + + ret = uclass_get_device(UCLASS_RTC, 0, &dev); + if (ret) { + debug("Cannot find RTC: err=%d\n", ret); + return -ENODEV; + } + + /* Save the stack address to CMOS */ + rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp); + + return 0; +} +#endif + int x86_fsp_init(void) { void *nvs; + int stack = CONFIG_FSP_TEMP_RAM_ADDR; int boot_mode = BOOT_FULL_CONFIG; #ifdef CONFIG_HAVE_ACPI_RESUME int prev_sleep_state = chipset_prev_sleep_state(); @@ -102,6 +129,7 @@ int x86_fsp_init(void) panic("Reboot System"); } + stack = cmos_read32(CMOS_FSP_STACK_ADDR); boot_mode = BOOT_ON_S3_RESUME; } #endif @@ -110,7 +138,7 @@ int x86_fsp_init(void) * Note the execution does not return to this function, * instead it jumps to fsp_continue(). */ - fsp_init(CONFIG_FSP_TEMP_RAM_ADDR, boot_mode, nvs); + fsp_init(stack, boot_mode, nvs); } else { /* * The second time we enter here, adjust the size of malloc()