diff mbox

[ARM] Cleanup macro TARGET_EITHER

Message ID VI1PR08MB0640EB037B2008CB88E87D2D98260@VI1PR08MB0640.eurprd08.prod.outlook.com
State New
Headers show

Commit Message

Sudakshina Das March 16, 2017, 11:11 a.m. UTC 
Hi all

This is a cleanup patch to remove the macro TARGET_EITHER. This macro seems to have become irrelevant in recent times since its previous definition had been commented out and replaced with 1.

Bootstrapped and tested on arm-none-linux-gnueabihf.

Sudi

2017-03-10  Sudakshina Das  <sudi.das@arm.com>

	* config/arm/arm.h (TARGET_EITHER): Delete.
	* config/arm/arm.md: Delete instances of TARGET_EITHER.

Comments

Kyrill Tkachov March 17, 2017, 12:22 p.m. UTC | #1 
Hi Sudi,

On 16/03/17 11:11, Sudi Das wrote:
>
> Hi all
>
> This is a cleanup patch to remove the macro TARGET_EITHER. This macro seems to have become irrelevant in recent times since its previous definition had been commented out and replaced with 1.
>
> Bootstrapped and tested on arm-none-linux-gnueabihf.
>

I've had my eye on that cleanup for some time now, thanks for doing this.
This patch is ok.
Seeing as we're close to the GCC 7 release and this is not a regression fix
I'd rather hold off applying it until after the release, so I've put this in
my queue of things to commit then.

Thanks,
Kyrill

> Sudi
>
> 2017-03-10  Sudakshina Das  <sudi.das@arm.com>
>
>         * config/arm/arm.h (TARGET_EITHER): Delete.
>         * config/arm/arm.md: Delete instances of TARGET_EITHER.
Richard Earnshaw (lists) March 17, 2017, 1:11 p.m. UTC | #2 
On 17/03/17 12:22, Kyrill Tkachov wrote:
> Hi Sudi,
> 
> On 16/03/17 11:11, Sudi Das wrote:
>>
>> Hi all
>>
>> This is a cleanup patch to remove the macro TARGET_EITHER. This macro
>> seems to have become irrelevant in recent times since its previous
>> definition had been commented out and replaced with 1.
>>
>> Bootstrapped and tested on arm-none-linux-gnueabihf.
>>
> 
> I've had my eye on that cleanup for some time now, thanks for doing this.
> This patch is ok.
> Seeing as we're close to the GCC 7 release and this is not a regression fix
> I'd rather hold off applying it until after the release, so I've put
> this in
> my queue of things to commit then.
> 
> Thanks,
> Kyrill
> 
>> Sudi
>>
>> 2017-03-10  Sudakshina Das  <sudi.das@arm.com>
>>
>>         * config/arm/arm.h (TARGET_EITHER): Delete.
>>         * config/arm/arm.md: Delete instances of TARGET_EITHER.
> 

The point of TARGET_EITHER was mostly to document that the operation was
deliberately enabled in all compilation modes and that leaving out a
choice of TARGET32 vs Thumb1 was not accidental.  As such, it's more
documentation than necessary code.

Does this really affect the performance/behaviour of the compiler?  If
it doesn't then I'd be in favour of leaving it as is.

R.
Kyrill Tkachov March 17, 2017, 2:02 p.m. UTC | #3 
Hi Richard,

On 17/03/17 13:11, Richard Earnshaw (lists) wrote:
> On 17/03/17 12:22, Kyrill Tkachov wrote:
>> Hi Sudi,
>>
>> On 16/03/17 11:11, Sudi Das wrote:
>>> Hi all
>>>
>>> This is a cleanup patch to remove the macro TARGET_EITHER. This macro
>>> seems to have become irrelevant in recent times since its previous
>>> definition had been commented out and replaced with 1.
>>>
>>> Bootstrapped and tested on arm-none-linux-gnueabihf.
>>>
>> I've had my eye on that cleanup for some time now, thanks for doing this.
>> This patch is ok.
>> Seeing as we're close to the GCC 7 release and this is not a regression fix
>> I'd rather hold off applying it until after the release, so I've put
>> this in
>> my queue of things to commit then.
>>
>> Thanks,
>> Kyrill
>>
>>> Sudi
>>>
>>> 2017-03-10  Sudakshina Das  <sudi.das@arm.com>
>>>
>>>          * config/arm/arm.h (TARGET_EITHER): Delete.
>>>          * config/arm/arm.md: Delete instances of TARGET_EITHER.
> The point of TARGET_EITHER was mostly to document that the operation was
> deliberately enabled in all compilation modes and that leaving out a
> choice of TARGET32 vs Thumb1 was not accidental.  As such, it's more
> documentation than necessary code.
>
> Does this really affect the performance/behaviour of the compiler?  If
> it doesn't then I'd be in favour of leaving it as is.

Looking at the usages of TARGET_EITHER I don't see any pattern where it looks
particularly enlightening. Some patterns gated on TARGET_EITHER have, immediately after that,
an
if (TARGET_32BIT)
  ...
else
  ...

path which makes it obvious that it handles all configurations anyway.
Some of the uses are gating fairly straightforward standard names like ashlsi3, negsi2
and saying that they are available for all configurations is not very helpful IMO as you'd
expect those fundamental patterns to be always available anyway.

Finally, TARGET_EITHER is not a particularly helpful name IMO. For a reader that would
in theory need the extra documentation, it doesn't convey what is it an EITHER *of*
(in this case 32-bit ARM/Thumb or 16-bit Thumb), they'd still need to look it up
in arm.h to see that this is what it means rather than an either of "VFP vs NEON"
or "softfloat vs hardfloat ABI" or some other binary choice in the arm backend.

Is there any particular usage of TARGET_EITHER that looks useful as documentation?
If so, I'd suggest we add a comment there clarifying it and still remove the TARGET_EITHER.

Thanks,
Kyrill

> R.
diff mbox

Patch

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index e95eda3..6afb54b 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -130,7 +130,6 @@  extern tree arm_fp16_type_node;
 #define TARGET_REALLY_IWMMXT2		(TARGET_IWMMXT2 && TARGET_32BIT)
 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT)
 #define TARGET_ARM                      (! TARGET_THUMB)
-#define TARGET_EITHER			1 /* (TARGET_ARM | TARGET_THUMB) */
 #define TARGET_BACKTRACE	        (crtl->is_leaf \
 				         ? TARGET_TPCS_LEAF_FRAME \
 				         : TARGET_TPCS_FRAME)
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 8720a71..3d9a09f 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -448,7 +448,7 @@ 
 	  (plus:DI (match_operand:DI 1 "s_register_operand" "")
 	           (match_operand:DI 2 "arm_adddi_operand"  "")))
     (clobber (reg:CC CC_REGNUM))])]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_THUMB1)
     {
@@ -577,7 +577,7 @@ 
   [(set (match_operand:SI          0 "s_register_operand" "")
 	(plus:SI (match_operand:SI 1 "s_register_operand" "")
 		 (match_operand:SI 2 "reg_or_int_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_32BIT && CONST_INT_P (operands[2]))
     {
@@ -1254,7 +1254,7 @@ 
 	  (minus:DI (match_operand:DI 1 "s_register_operand" "")
 	            (match_operand:DI 2 "s_register_operand" "")))
     (clobber (reg:CC CC_REGNUM))])]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_THUMB1)
     {
@@ -1430,7 +1430,7 @@ 
   [(set (match_operand:SI           0 "s_register_operand" "")
 	(minus:SI (match_operand:SI 1 "reg_or_int_operand" "")
 		  (match_operand:SI 2 "s_register_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   if (CONST_INT_P (operands[1]))
     {
@@ -1566,7 +1566,7 @@ 
   [(set (match_operand:SI          0 "s_register_operand" "")
 	(mult:SI (match_operand:SI 2 "s_register_operand" "")
 		 (match_operand:SI 1 "s_register_operand" "")))]
-  "TARGET_EITHER"
+  ""
   ""
 )
 
@@ -2345,7 +2345,7 @@ 
   [(set (match_operand:SI         0 "s_register_operand" "")
 	(and:SI (match_operand:SI 1 "s_register_operand" "")
 		(match_operand:SI 2 "reg_or_int_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_32BIT)
     {
@@ -3210,7 +3210,7 @@ 
   [(set (match_operand:SI         0 "s_register_operand" "")
 	(ior:SI (match_operand:SI 1 "s_register_operand" "")
 		(match_operand:SI 2 "reg_or_int_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   if (CONST_INT_P (operands[2]))
     {
@@ -3394,7 +3394,7 @@ 
   [(set (match_operand:SI         0 "s_register_operand" "")
 	(xor:SI (match_operand:SI 1 "s_register_operand" "")
 		(match_operand:SI 2 "reg_or_int_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "if (CONST_INT_P (operands[2]))
     {
       if (TARGET_32BIT)
@@ -4052,7 +4052,7 @@ 
   [(set (match_operand:SI            0 "s_register_operand" "")
 	(ashift:SI (match_operand:SI 1 "s_register_operand" "")
 		   (match_operand:SI 2 "arm_rhs_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   if (CONST_INT_P (operands[2])
       && (UINTVAL (operands[2])) > 31)
@@ -4121,7 +4121,7 @@ 
   [(set (match_operand:SI              0 "s_register_operand" "")
 	(ashiftrt:SI (match_operand:SI 1 "s_register_operand" "")
 		     (match_operand:SI 2 "arm_rhs_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   if (CONST_INT_P (operands[2])
       && UINTVAL (operands[2]) > 31)
@@ -4187,7 +4187,7 @@ 
   [(set (match_operand:SI              0 "s_register_operand" "")
 	(lshiftrt:SI (match_operand:SI 1 "s_register_operand" "")
 		     (match_operand:SI 2 "arm_rhs_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   if (CONST_INT_P (operands[2])
       && (UINTVAL (operands[2])) > 31)
@@ -4219,7 +4219,7 @@ 
   [(set (match_operand:SI              0 "s_register_operand" "")
 	(rotatert:SI (match_operand:SI 1 "s_register_operand" "")
 		     (match_operand:SI 2 "arm_rhs_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_32BIT)
     {
@@ -4677,7 +4677,7 @@ 
    [(set (match_operand:DI 0 "s_register_operand" "")
 	 (neg:DI (match_operand:DI 1 "s_register_operand" "")))
     (clobber (reg:CC CC_REGNUM))])]
-  "TARGET_EITHER"
+  ""
   {
     if (TARGET_NEON)
       {
@@ -4730,7 +4730,7 @@ 
 (define_expand "negsi2"
   [(set (match_operand:SI         0 "s_register_operand" "")
 	(neg:SI (match_operand:SI 1 "s_register_operand" "")))]
-  "TARGET_EITHER"
+  ""
   ""
 )
 
@@ -4882,7 +4882,7 @@ 
     [(set (match_operand:SI         0 "s_register_operand" "")
 	  (abs:SI (match_operand:SI 1 "s_register_operand" "")))
      (clobber (match_dup 2))])]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_THUMB1)
     operands[2] = gen_rtx_SCRATCH (SImode);
@@ -5060,7 +5060,7 @@ 
 (define_expand "one_cmplsi2"
   [(set (match_operand:SI         0 "s_register_operand" "")
 	(not:SI (match_operand:SI 1 "s_register_operand" "")))]
-  "TARGET_EITHER"
+  ""
   ""
 )
 
@@ -5104,7 +5104,7 @@ 
 (define_expand "floatsihf2"
   [(set (match_operand:HF           0 "general_operand" "")
 	(float:HF (match_operand:SI 1 "general_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   {
     rtx op1 = gen_reg_rtx (SFmode);
@@ -5118,7 +5118,7 @@ 
 (define_expand "floatdihf2"
   [(set (match_operand:HF           0 "general_operand" "")
 	(float:HF (match_operand:DI 1 "general_operand" "")))]
-  "TARGET_EITHER"
+  ""
   "
   {
     rtx op1 = gen_reg_rtx (SFmode);
@@ -5146,7 +5146,7 @@ 
 (define_expand "fix_trunchfsi2"
   [(set (match_operand:SI         0 "general_operand" "")
 	(fix:SI (fix:HF (match_operand:HF 1 "general_operand"  ""))))]
-  "TARGET_EITHER"
+  ""
   "
   {
     rtx op1 = convert_to_mode (SFmode, operands[1], 0);
@@ -5158,7 +5158,7 @@ 
 (define_expand "fix_trunchfdi2"
   [(set (match_operand:DI         0 "general_operand" "")
 	(fix:DI (fix:HF (match_operand:HF 1 "general_operand"  ""))))]
-  "TARGET_EITHER"
+  ""
   "
   {
     rtx op1 = convert_to_mode (SFmode, operands[1], 0);
@@ -5202,7 +5202,7 @@ 
   [(set (match_operand:HF  0 "s_register_operand" "")
 	(float_truncate:HF
 	 (match_operand:DF 1 "s_register_operand" "")))]
-  "(TARGET_EITHER && flag_unsafe_math_optimizations)
+  "flag_unsafe_math_optimizations
    || (TARGET_32BIT && TARGET_FP16_TO_DOUBLE)"
 {
   /* We don't have a direct instruction for this, so we must be in
@@ -5306,7 +5306,7 @@ 
 (define_expand "zero_extendhisi2"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  "TARGET_EITHER"
+  ""
 {
   if (TARGET_ARM && !arm_arch4 && MEM_P (operands[1]))
     {
@@ -5369,7 +5369,7 @@ 
 (define_expand "zero_extendqisi2"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
-  "TARGET_EITHER"
+  ""
 {
   if (TARGET_ARM && !arm_arch6 && !MEM_P (operands[1]))
     {
@@ -5493,7 +5493,7 @@ 
 (define_expand "extendhisi2"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
-  "TARGET_EITHER"
+  ""
 {
   if (TARGET_THUMB1)
     {
@@ -5645,7 +5645,7 @@ 
 (define_expand "extendqisi2"
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(sign_extend:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")))]
-  "TARGET_EITHER"
+  ""
 {
   if (!arm_arch4 && MEM_P (operands[1]))
     operands[1] = copy_to_mode_reg (QImode, operands[1]);
@@ -5720,7 +5720,7 @@ 
 (define_expand "extendhfdf2"
   [(set (match_operand:DF		   0 "s_register_operand" "")
 	(float_extend:DF (match_operand:HF 1 "s_register_operand" "")))]
-  "TARGET_EITHER"
+  ""
 {
   /* We don't have a direct instruction for this, so go via SFmode.  */
   if (!(TARGET_32BIT && TARGET_FP16_TO_DOUBLE))
@@ -5800,7 +5800,7 @@ 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "general_operand" "")
 	(match_operand:DI 1 "general_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   if (can_create_pseudo_p ())
     {
@@ -5921,7 +5921,7 @@ 
 (define_split
   [(set (match_operand:ANY64 0 "arm_general_register_operand" "")
 	(match_operand:ANY64 1 "arm_general_register_operand" ""))]
-  "TARGET_EITHER && reload_completed"
+  "reload_completed"
   [(set (match_dup 0) (match_dup 1))
    (set (match_dup 2) (match_dup 3))]
   "
@@ -5967,7 +5967,7 @@ 
 (define_expand "movsi"
   [(set (match_operand:SI 0 "general_operand" "")
         (match_operand:SI 1 "general_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   {
   rtx base, offset, tmp;
@@ -6483,7 +6483,7 @@ 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "general_operand" "")
 	(match_operand:HI 1 "general_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_ARM)
     {
@@ -6767,7 +6767,7 @@ 
   [(parallel [(match_operand:HI 0 "arm_reload_memory_operand" "=o")
 	      (match_operand:HI 1 "s_register_operand"        "r")
 	      (match_operand:DI 2 "s_register_operand"        "=&l")])]
-  "TARGET_EITHER"
+  ""
   "if (TARGET_ARM)
      arm_reload_out_hi (operands);
    else
@@ -6780,7 +6780,7 @@ 
   [(parallel [(match_operand:HI 0 "s_register_operand" "=r")
 	      (match_operand:HI 1 "arm_reload_memory_operand" "o")
 	      (match_operand:DI 2 "s_register_operand" "=&r")])]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_ARM)
     arm_reload_in_hi (operands);
@@ -6792,7 +6792,7 @@ 
 (define_expand "movqi"
   [(set (match_operand:QI 0 "general_operand" "")
         (match_operand:QI 1 "general_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   /* Everything except mem = const or mem = mem can be done easily */
 
@@ -6890,7 +6890,7 @@ 
 (define_expand "movhf"
   [(set (match_operand:HF 0 "general_operand" "")
 	(match_operand:HF 1 "general_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_32BIT)
     {
@@ -6955,7 +6955,7 @@ 
 (define_expand "movsf"
   [(set (match_operand:SF 0 "general_operand" "")
 	(match_operand:SF 1 "general_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_32BIT)
     {
@@ -6978,8 +6978,7 @@ 
 (define_split
   [(set (match_operand:SF 0 "arm_general_register_operand" "")
 	(match_operand:SF 1 "immediate_operand" ""))]
-  "TARGET_EITHER
-   && reload_completed
+  "reload_completed
    && CONST_DOUBLE_P (operands[1])"
   [(set (match_dup 2) (match_dup 3))]
   "
@@ -7013,7 +7012,7 @@ 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "general_operand" "")
 	(match_operand:DF 1 "general_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   if (TARGET_32BIT)
     {
@@ -7231,7 +7230,7 @@ 
 	        (match_operand:SI 2 "nonmemory_operand" "")])
 	      (label_ref (match_operand 3 "" ""))
 	      (pc)))]
-  "TARGET_EITHER"
+  ""
   "
   if (!TARGET_THUMB1)
     {
@@ -8023,7 +8022,7 @@ 
 (define_expand "jump"
   [(set (pc)
 	(label_ref (match_operand 0 "" "")))]
-  "TARGET_EITHER"
+  ""
   ""
 )
 
@@ -8057,7 +8056,7 @@ 
 	            (match_operand 1 "general_operand" ""))
 	      (use (match_operand 2 "" ""))
 	      (clobber (reg:SI LR_REGNUM))])]
-  "TARGET_EITHER"
+  ""
   "
   {
     rtx callee, pat;
@@ -8146,7 +8145,7 @@ 
 		         (match_operand 2 "general_operand" "")))
 	      (use (match_operand 3 "" ""))
 	      (clobber (reg:SI LR_REGNUM))])]
-  "TARGET_EITHER"
+  ""
   "
   {
     rtx pat, callee;
@@ -8520,7 +8519,7 @@ 
 		    (const_int 0))
 	      (match_operand 1 "" "")
 	      (match_operand 2 "" "")])]
-  "TARGET_EITHER"
+  ""
   "
   {
     int i;
@@ -8587,7 +8586,7 @@ 
 (define_expand "untyped_return"
   [(match_operand:BLK 0 "memory_operand" "")
    (match_operand 1 "" "")]
-  "TARGET_EITHER"
+  ""
   "
   {
     int i;
@@ -8637,7 +8636,7 @@ 
 
 (define_insn "blockage"
   [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
-  "TARGET_EITHER"
+  ""
   ""
   [(set_attr "length" "0")
    (set_attr "type" "block")]
@@ -8729,7 +8728,7 @@ 
 (define_expand "indirect_jump"
   [(set (pc)
 	(match_operand:SI 0 "s_register_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   /* Thumb-2 doesn't have mov pc, reg.  Explicitly set the low bit of the
      address and use bx.  */
@@ -8769,7 +8768,7 @@ 
 
 (define_insn "nop"
   [(const_int 0)]
-  "TARGET_EITHER"
+  ""
   "nop"
   [(set (attr "length")
 	(if_then_else (eq_attr "is_thumb" "yes")
@@ -10724,7 +10723,7 @@ 
 
 (define_expand "prologue"
   [(clobber (const_int 0))]
-  "TARGET_EITHER"
+  ""
   "if (TARGET_32BIT)
      arm_expand_prologue ();
    else
@@ -10735,7 +10734,7 @@ 
 
 (define_expand "epilogue"
   [(clobber (const_int 0))]
-  "TARGET_EITHER"
+  ""
   "
   if (crtl->calls_eh_return)
     emit_insn (gen_force_register_use (gen_rtx_REG (Pmode, 2)));
@@ -10778,7 +10777,7 @@ 
   [(use (match_operand:SI 0 "register_operand" ""))
    (use (match_operand:SI 1 "register_operand" ""))
    (use (match_operand:SI 2 "register_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   {
     cfun->machine->eh_epilogue_sp_ofs = operands[1];
@@ -11164,7 +11163,7 @@ 
 
 (define_insn "align_4"
   [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN)]
-  "TARGET_EITHER"
+  ""
   "*
   assemble_align (32);
   return \"\";
@@ -11174,7 +11173,7 @@ 
 
 (define_insn "align_8"
   [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN8)]
-  "TARGET_EITHER"
+  ""
   "*
   assemble_align (64);
   return \"\";
@@ -11184,7 +11183,7 @@ 
 
 (define_insn "consttable_end"
   [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
-  "TARGET_EITHER"
+  ""
   "*
   making_const_table = FALSE;
   return \"\";
@@ -11194,7 +11193,7 @@ 
 
 (define_insn "consttable_1"
   [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_1)]
-  "TARGET_EITHER"
+  ""
   "*
   making_const_table = TRUE;
   assemble_integer (operands[0], 1, BITS_PER_WORD, 1);
@@ -11207,7 +11206,7 @@ 
 
 (define_insn "consttable_2"
   [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_2)]
-  "TARGET_EITHER"
+  ""
   "*
   {
     rtx x = operands[0];
@@ -11230,7 +11229,7 @@ 
 
 (define_insn "consttable_4"
   [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_4)]
-  "TARGET_EITHER"
+  ""
   "*
   {
     rtx x = operands[0];
@@ -11261,7 +11260,7 @@ 
 
 (define_insn "consttable_8"
   [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_8)]
-  "TARGET_EITHER"
+  ""
   "*
   {
     making_const_table = TRUE;
@@ -11283,7 +11282,7 @@ 
 
 (define_insn "consttable_16"
   [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_16)]
-  "TARGET_EITHER"
+  ""
   "*
   {
     making_const_table = TRUE;
@@ -11376,7 +11375,7 @@ 
 
 (define_expand "eh_return"
   [(use (match_operand 0 "general_operand" ""))]
-  "TARGET_EITHER"
+  ""
   "
   {
     if (TARGET_32BIT)
@@ -11620,7 +11619,7 @@ 
 (define_expand "bswapsi2"
   [(set (match_operand:SI 0 "s_register_operand" "=r")
   	(bswap:SI (match_operand:SI 1 "s_register_operand" "r")))]
-"TARGET_EITHER && (arm_arch6 || !optimize_size)"
+"arm_arch6 || !optimize_size"
 "
     if (!arm_arch6)
       {