From patchwork Thu Mar 16 10:32:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aneesh Kumar K.V" X-Patchwork-Id: 739761 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vkQDF2kPfz9rxw for ; Thu, 16 Mar 2017 21:47:57 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vkQDF1hWbzDr4n for ; Thu, 16 Mar 2017 21:47:57 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vkPvC6D3czDqYR for ; Thu, 16 Mar 2017 21:33:11 +1100 (AEDT) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v2GANgiq060718 for ; Thu, 16 Mar 2017 06:33:00 -0400 Received: from e15.ny.us.ibm.com (e15.ny.us.ibm.com [129.33.205.205]) by mx0b-001b2d01.pphosted.com with ESMTP id 2978frjpvr-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 16 Mar 2017 06:32:59 -0400 Received: from localhost by e15.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 16 Mar 2017 06:32:56 -0400 Received: from b01ledav03.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v2GAWuel45547648; Thu, 16 Mar 2017 10:32:56 GMT Received: from b01ledav03.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 710C7B204D; Thu, 16 Mar 2017 06:32:52 -0400 (EDT) Received: from skywalker.in.ibm.com (unknown [9.124.35.129]) by b01ledav03.gho.pok.ibm.com (Postfix) with ESMTP id 9CC10B2066; Thu, 16 Mar 2017 06:32:50 -0400 (EDT) From: "Aneesh Kumar K.V" To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au Subject: [PATCH V2 11/11] powerpc/mm: Move hash specific pte bits to be top bits of RPN Date: Thu, 16 Mar 2017 16:02:09 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489660329-22501-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> References: <1489660329-22501-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17031610-0036-0000-0000-000001B12731 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006792; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000206; SDB=6.00834596; UDB=6.00409881; IPR=6.00612250; BA=6.00005214; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00014671; XFM=3.00000013; UTC=2017-03-16 10:32:58 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17031610-0037-0000-0000-00003EF05CEB Message-Id: <1489660329-22501-12-git-send-email-aneesh.kumar@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-16_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703160084 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" We don't support the full 57 bits of physical address and hence can overload the top bits of RPN as hash specific pte bits. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash.h | 18 ++++++------------ arch/powerpc/include/asm/book3s/64/pgtable.h | 19 ++++++++++++++++--- arch/powerpc/mm/hash_native_64.c | 1 + 3 files changed, 23 insertions(+), 15 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h index af3c88624d3a..33eb1a650317 100644 --- a/arch/powerpc/include/asm/book3s/64/hash.h +++ b/arch/powerpc/include/asm/book3s/64/hash.h @@ -6,20 +6,14 @@ * Common bits between 4K and 64K pages in a linux-style PTE. * Additional bits may be defined in pgtable-hash64-*.h * - * Note: We only support user read/write permissions. Supervisor always - * have full read/write to pages above PAGE_OFFSET (pages below that - * always use the user access permissions). - * - * We could create separate kernel read-only if we used the 3 PP bits - * combinations that newer processors provide but we currently don't. */ -#define H_PAGE_BUSY _RPAGE_SW1 /* software: PTE & hash are busy */ +#define H_PAGE_BUSY _RPAGE_RPN45 /* software: PTE & hash are busy */ #define H_PTE_NONE_MASK _PAGE_HPTEFLAGS -#define H_PAGE_F_GIX_SHIFT 57 -/* (7ul << 57) HPTE index within HPTEG */ -#define H_PAGE_F_GIX (_RPAGE_RSV2 | _RPAGE_RSV3 | _RPAGE_RSV4) -#define H_PAGE_F_SECOND _RPAGE_RSV1 /* HPTE is in 2ndary HPTEG */ -#define H_PAGE_HASHPTE _RPAGE_SW0 /* PTE has associated HPTE */ +#define H_PAGE_F_GIX_SHIFT 52 +/* (7ul << 53) HPTE index within HPTEG */ +#define H_PAGE_F_SECOND _RPAGE_RPN44 /* HPTE is in 2ndary HPTEG */ +#define H_PAGE_F_GIX (_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41) +#define H_PAGE_HASHPTE _RPAGE_RPN40 /* PTE has associated HPTE */ /* * Max physical address bit we will use for now. * diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h index eb82b60b5c89..3d104f8ad891 100644 --- a/arch/powerpc/include/asm/book3s/64/pgtable.h +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h @@ -36,16 +36,29 @@ #define _RPAGE_RSV2 0x0800000000000000UL #define _RPAGE_RSV3 0x0400000000000000UL #define _RPAGE_RSV4 0x0200000000000000UL + +#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ +#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ + +/* + * Top and bottom bits of RPN which can be used by hash + * translation mode, because we expect them to be zero + * otherwise. + */ #define _RPAGE_RPN0 0x01000 #define _RPAGE_RPN1 0x02000 +#define _RPAGE_RPN45 0x0100000000000000UL +#define _RPAGE_RPN44 0x0080000000000000UL +#define _RPAGE_RPN43 0x0040000000000000UL +#define _RPAGE_RPN42 0x0020000000000000UL +#define _RPAGE_RPN41 0x0010000000000000UL +#define _RPAGE_RPN40 0x0008000000000000UL + /* Max physicall address bit as per radix table */ #define _RPAGE_PA_MAX 57 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ - -#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */ -#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */ /* * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE * Instead of fixing all of them, add an alternate define which diff --git a/arch/powerpc/mm/hash_native_64.c b/arch/powerpc/mm/hash_native_64.c index cc332608e656..917a5a336441 100644 --- a/arch/powerpc/mm/hash_native_64.c +++ b/arch/powerpc/mm/hash_native_64.c @@ -246,6 +246,7 @@ static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn, __asm__ __volatile__ ("ptesync" : : : "memory"); + BUILD_BUG_ON(H_PAGE_F_SECOND != (1ul << (H_PAGE_F_GIX_SHIFT + 3))); return i | (!!(vflags & HPTE_V_SECONDARY) << 3); }