From patchwork Thu Mar 16 10:32:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Aneesh Kumar K.V" X-Patchwork-Id: 739760 Return-Path: X-Original-To: patchwork-incoming@ozlabs.org Delivered-To: patchwork-incoming@ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vkQBx3Cgjz9rxw for ; Thu, 16 Mar 2017 21:46:49 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vkQBx2SKrzDrJZ for ; Thu, 16 Mar 2017 21:46:49 +1100 (AEDT) X-Original-To: linuxppc-dev@lists.ozlabs.org Delivered-To: linuxppc-dev@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vkPvC3qjVzDqb5 for ; Thu, 16 Mar 2017 21:33:11 +1100 (AEDT) Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v2GANjoN011635 for ; Thu, 16 Mar 2017 06:32:58 -0400 Received: from e16.ny.us.ibm.com (e16.ny.us.ibm.com [129.33.205.206]) by mx0a-001b2d01.pphosted.com with ESMTP id 2978fjar0x-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 16 Mar 2017 06:32:57 -0400 Received: from localhost by e16.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 16 Mar 2017 06:32:53 -0400 Received: from b01ledav03.gho.pok.ibm.com (b01ledav003.gho.pok.ibm.com [9.57.199.108]) by b01cxnp23032.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v2GAWqY539780522; Thu, 16 Mar 2017 10:32:52 GMT Received: from b01ledav03.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 27CF2B2065; Thu, 16 Mar 2017 06:32:49 -0400 (EDT) Received: from skywalker.in.ibm.com (unknown [9.124.35.129]) by b01ledav03.gho.pok.ibm.com (Postfix) with ESMTP id 5504DB204D; Thu, 16 Mar 2017 06:32:47 -0400 (EDT) From: "Aneesh Kumar K.V" To: benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au Subject: [PATCH V2 10/11] powerpc/mm/radix: Make max pfn bits a variable Date: Thu, 16 Mar 2017 16:02:08 +0530 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489660329-22501-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> References: <1489660329-22501-1-git-send-email-aneesh.kumar@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17031610-0024-0000-0000-00000218253D X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006792; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000206; SDB=6.00834596; UDB=6.00409880; IPR=6.00612250; BA=6.00005214; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00014671; XFM=3.00000013; UTC=2017-03-16 10:32:55 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17031610-0025-0000-0000-0000429958A3 Message-Id: <1489660329-22501-11-git-send-email-aneesh.kumar@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-16_09:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703160084 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linuxppc-dev@lists.ozlabs.org, "Aneesh Kumar K.V" Errors-To: linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org Sender: "Linuxppc-dev" This makes max pysical address bits a variable so that hash and radix translation mode can choose what value to use. In this patch we also switch the radix translation mode to use 57 bits. This make it resilient to future changes to max pfn supported by platforms. This patch is split from the previous one to make the review easier. Signed-off-by: Aneesh Kumar K.V --- arch/powerpc/include/asm/book3s/64/hash.h | 18 ++++++++++++++++++ arch/powerpc/include/asm/book3s/64/pgtable.h | 28 +++++----------------------- arch/powerpc/include/asm/book3s/64/radix.h | 4 ++++ arch/powerpc/mm/hash_utils_64.c | 1 + arch/powerpc/mm/pgtable-radix.c | 1 + arch/powerpc/mm/pgtable_64.c | 3 +++ 6 files changed, 32 insertions(+), 23 deletions(-) diff --git a/arch/powerpc/include/asm/book3s/64/hash.h b/arch/powerpc/include/asm/book3s/64/hash.h index ec2828b1db07..af3c88624d3a 100644 --- a/arch/powerpc/include/asm/book3s/64/hash.h +++ b/arch/powerpc/include/asm/book3s/64/hash.h @@ -20,6 +20,24 @@ #define H_PAGE_F_GIX (_RPAGE_RSV2 | _RPAGE_RSV3 | _RPAGE_RSV4) #define H_PAGE_F_SECOND _RPAGE_RSV1 /* HPTE is in 2ndary HPTEG */ #define H_PAGE_HASHPTE _RPAGE_SW0 /* PTE has associated HPTE */ +/* + * Max physical address bit we will use for now. + * + * This is mostly a hardware limitation and for now Power9 has + * a 51 bit limit. + * + * This is different from the number of physical bit required to address + * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. + * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum + * number of sections we can support (SECTIONS_SHIFT). + * + * This is different from Radix page table limitation and + * should always be less than that. The limit is done such that + * we can overload the bits between _RPAGE_PA_MAX and H_PAGE_PA_MAX + * for hash linux page table specific bits. + */ +#define H_PAGE_PA_MAX 51 +#define H_PTE_RPN_MASK (((1UL << H_PAGE_PA_MAX) - 1) & (PAGE_MASK)) #ifdef CONFIG_PPC_64K_PAGES #include diff --git a/arch/powerpc/include/asm/book3s/64/pgtable.h b/arch/powerpc/include/asm/book3s/64/pgtable.h index c470dcc815d5..eb82b60b5c89 100644 --- a/arch/powerpc/include/asm/book3s/64/pgtable.h +++ b/arch/powerpc/include/asm/book3s/64/pgtable.h @@ -40,23 +40,6 @@ #define _RPAGE_RPN1 0x02000 /* Max physicall address bit as per radix table */ #define _RPAGE_PA_MAX 57 -/* - * Max physical address bit we will use for now. - * - * This is mostly a hardware limitation and for now Power9 has - * a 51 bit limit. - * - * This is different from the number of physical bit required to address - * the last byte of memory. That is defined by MAX_PHYSMEM_BITS. - * MAX_PHYSMEM_BITS is a linux limitation imposed by the maximum - * number of sections we can support (SECTIONS_SHIFT). - * - * This is different from Radix page table limitation above and - * should always be less than that. The limit is done such that - * we can overload the bits between _RPAGE_PA_MAX and _PAGE_PA_MAX - * for hash linux page table specific bits. - */ -#define _PAGE_PA_MAX 51 #define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */ #define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */ @@ -70,12 +53,6 @@ */ #define _PAGE_NO_CACHE _PAGE_TOLERANT /* - * We support _RPAGE_PA_MAX bit real address in pte. On the linux side - * we are limited by _PAGE_PA_MAX. Clear everything above _PAGE_PA_MAX - * every thing below PAGE_SHIFT; - */ -#define PTE_RPN_MASK (((1UL << _PAGE_PA_MAX) - 1) & (PAGE_MASK)) -/* * set of bits not changed in pmd_modify. Even though we have hash specific bits * in here, on radix we expect them to be zero. */ @@ -180,6 +157,11 @@ #ifndef __ASSEMBLY__ /* + * based on max physical address bit that we want to encode in page table + */ +extern unsigned long __pte_rpn_mask; +#define PTE_RPN_MASK __pte_rpn_mask +/* * page table defines */ extern unsigned long __pte_index_size; diff --git a/arch/powerpc/include/asm/book3s/64/radix.h b/arch/powerpc/include/asm/book3s/64/radix.h index ac16d1943022..142739b31174 100644 --- a/arch/powerpc/include/asm/book3s/64/radix.h +++ b/arch/powerpc/include/asm/book3s/64/radix.h @@ -24,6 +24,10 @@ /* An empty PTE can still have a R or C writeback */ #define RADIX_PTE_NONE_MASK (_PAGE_DIRTY | _PAGE_ACCESSED) +/* + * Clear everything above _RPAGE_PA_MAX every thing below PAGE_SHIFT + */ +#define RADIX_PTE_RPN_MASK (((1UL << _RPAGE_PA_MAX) - 1) & (PAGE_MASK)) /* Bits to set in a RPMD/RPUD/RPGD */ #define RADIX_PMD_VAL_BITS (0x8000000000000000UL | RADIX_PTE_INDEX_SIZE) diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index c554768b1fa2..d990c3332057 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -986,6 +986,7 @@ void __init hash__early_init_mmu(void) /* * initialize page table size */ + __pte_rpn_mask = H_PTE_RPN_MASK; __pte_frag_nr = H_PTE_FRAG_NR; __pte_frag_size_shift = H_PTE_FRAG_SIZE_SHIFT; diff --git a/arch/powerpc/mm/pgtable-radix.c b/arch/powerpc/mm/pgtable-radix.c index c28165d8970b..6eecbbc7c8af 100644 --- a/arch/powerpc/mm/pgtable-radix.c +++ b/arch/powerpc/mm/pgtable-radix.c @@ -379,6 +379,7 @@ void __init radix__early_init_mmu(void) /* * initialize page table size */ + __pte_rpn_mask = RADIX_PTE_RPN_MASK; __pte_index_size = RADIX_PTE_INDEX_SIZE; __pmd_index_size = RADIX_PMD_INDEX_SIZE; __pud_index_size = RADIX_PUD_INDEX_SIZE; diff --git a/arch/powerpc/mm/pgtable_64.c b/arch/powerpc/mm/pgtable_64.c index db93cf747a03..ac0c7ee60de0 100644 --- a/arch/powerpc/mm/pgtable_64.c +++ b/arch/powerpc/mm/pgtable_64.c @@ -68,6 +68,9 @@ */ struct prtb_entry *process_tb; struct patb_entry *partition_tb; + +unsigned long __pte_rpn_mask; +EXPORT_SYMBOL(__pte_rpn_mask); /* * page table size */