From patchwork Wed Mar 15 17:46:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Keeping X-Patchwork-Id: 739391 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vk04c0R9Zz9s03 for ; Thu, 16 Mar 2017 05:09:52 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=metanate.com header.i=@metanate.com header.b="nELrafVw"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752976AbdCOSJv (ORCPT ); Wed, 15 Mar 2017 14:09:51 -0400 Received: from dougal.metanate.com ([90.155.101.14]:56047 "EHLO metanate.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752915AbdCOSJt (ORCPT ); Wed, 15 Mar 2017 14:09:49 -0400 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=simple/simple; d=metanate.com; s=stronger; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=eLkWNqlpiAN0DiYP4qINVj6/wcr2qrvKBn11JtYwbsQ=; b=nELrafVwGHhE3/1NlJOKhCEorjNrp/LGCNc8eHrclRB3/9sVfxvhXGuhAdTjCePvL5IVDzPmlJCg309wOY9h52SIZoTCBRRomOo/eFykhuxr/TvV9Def7PaGy1i26SFwDjCrr8hKRAhlJR16/ZG4E7OZfajn73NvO3iiCeo+fXI/W3SqQBBHrf93wxPRjDP8tZb1sw98wLja1ocsbU5Xtb6h0+5R/fkopE41XBML/KB7p6jvSPIC6KgTq3G8JRE69GaIE3aoA3YDklkREoGmv5JLANlT+zlY63FKrvyCv+okFr0SVKDt7EvTKQTxFsXikNXF9R1uv/pmNuw1pfxc0Q==; Received: from brian ([192.168.88.1] helo=leela.metanate.com) by shrek.metanate.com with esmtpsa (TLSv1.2:DHE-RSA-AES128-GCM-SHA256:128) (Exim 4.83_RC2) (envelope-from ) id 1coD0t-00055n-1S; Wed, 15 Mar 2017 17:47:07 +0000 From: John Keeping To: Heiko Stuebner Cc: Julia Cartwright , Linus Walleij , linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, John Keeping Subject: [PATCH v2 2/4] pinctrl: rockchip: convert to raw spinlock Date: Wed, 15 Mar 2017 17:46:52 +0000 Message-Id: <20170315174654.15128-3-john@metanate.com> X-Mailer: git-send-email 2.12.0.377.gf910686b23.dirty In-Reply-To: <20170315174654.15128-1-john@metanate.com> References: <20170315174654.15128-1-john@metanate.com> Sender: linux-gpio-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This lock is used from rockchip_irq_set_type() which is part of the irq_chip implementation and thus must use raw_spinlock_t as documented in Documentation/gpio/driver.txt. Signed-off-by: John Keeping Reviewed-by: Heiko Stuebner Tested-by: Heiko Stuebner --- v2: unchanged --- drivers/pinctrl/pinctrl-rockchip.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c index 128c383ea7ba..8c1cae6d78d7 100644 --- a/drivers/pinctrl/pinctrl-rockchip.c +++ b/drivers/pinctrl/pinctrl-rockchip.c @@ -163,7 +163,7 @@ struct rockchip_pin_bank { struct irq_domain *domain; struct gpio_chip gpio_chip; struct pinctrl_gpio_range grange; - spinlock_t slock; + raw_spinlock_t slock; u32 toggle_edge_mode; }; @@ -1295,14 +1295,14 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, switch (ctrl->type) { case RK2928: - spin_lock_irqsave(&bank->slock, flags); + raw_spin_lock_irqsave(&bank->slock, flags); data = BIT(bit + 16); if (pull == PIN_CONFIG_BIAS_DISABLE) data |= BIT(bit); ret = regmap_write(regmap, reg, data); - spin_unlock_irqrestore(&bank->slock, flags); + raw_spin_unlock_irqrestore(&bank->slock, flags); break; case RK1108: case RK3188: @@ -1503,7 +1503,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, return ret; clk_enable(bank->clk); - spin_lock_irqsave(&bank->slock, flags); + raw_spin_lock_irqsave(&bank->slock, flags); data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); /* set bit to 1 for output, 0 for input */ @@ -1513,7 +1513,7 @@ static int _rockchip_pmx_gpio_set_direction(struct gpio_chip *chip, data &= ~BIT(pin); writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); - spin_unlock_irqrestore(&bank->slock, flags); + raw_spin_unlock_irqrestore(&bank->slock, flags); clk_disable(bank->clk); return 0; @@ -1963,7 +1963,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) u32 data; clk_enable(bank->clk); - spin_lock_irqsave(&bank->slock, flags); + raw_spin_lock_irqsave(&bank->slock, flags); data = readl(reg); data &= ~BIT(offset); @@ -1971,7 +1971,7 @@ static void rockchip_gpio_set(struct gpio_chip *gc, unsigned offset, int value) data |= BIT(offset); writel(data, reg); - spin_unlock_irqrestore(&bank->slock, flags); + raw_spin_unlock_irqrestore(&bank->slock, flags); clk_disable(bank->clk); } @@ -2083,7 +2083,7 @@ static void rockchip_irq_demux(struct irq_desc *desc) data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT); do { - spin_lock_irqsave(&bank->slock, flags); + raw_spin_lock_irqsave(&bank->slock, flags); polarity = readl_relaxed(bank->reg_base + GPIO_INT_POLARITY); @@ -2094,7 +2094,7 @@ static void rockchip_irq_demux(struct irq_desc *desc) writel(polarity, bank->reg_base + GPIO_INT_POLARITY); - spin_unlock_irqrestore(&bank->slock, flags); + raw_spin_unlock_irqrestore(&bank->slock, flags); data_old = data; data = readl_relaxed(bank->reg_base + @@ -2125,20 +2125,20 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) return ret; clk_enable(bank->clk); - spin_lock_irqsave(&bank->slock, flags); + raw_spin_lock_irqsave(&bank->slock, flags); data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR); data &= ~mask; writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR); - spin_unlock_irqrestore(&bank->slock, flags); + raw_spin_unlock_irqrestore(&bank->slock, flags); if (type & IRQ_TYPE_EDGE_BOTH) irq_set_handler_locked(d, handle_edge_irq); else irq_set_handler_locked(d, handle_level_irq); - spin_lock_irqsave(&bank->slock, flags); + raw_spin_lock_irqsave(&bank->slock, flags); irq_gc_lock(gc); level = readl_relaxed(gc->reg_base + GPIO_INTTYPE_LEVEL); @@ -2181,7 +2181,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) break; default: irq_gc_unlock(gc); - spin_unlock_irqrestore(&bank->slock, flags); + raw_spin_unlock_irqrestore(&bank->slock, flags); clk_disable(bank->clk); return -EINVAL; } @@ -2190,7 +2190,7 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type) writel_relaxed(polarity, gc->reg_base + GPIO_INT_POLARITY); irq_gc_unlock(gc); - spin_unlock_irqrestore(&bank->slock, flags); + raw_spin_unlock_irqrestore(&bank->slock, flags); clk_disable(bank->clk); return 0; @@ -2472,7 +2472,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data( for (i = 0; i < ctrl->nr_banks; ++i, ++bank) { int bank_pins = 0; - spin_lock_init(&bank->slock); + raw_spin_lock_init(&bank->slock); bank->drvdata = d; bank->pin_base = ctrl->nr_pins; ctrl->nr_pins += bank->nr_pins;