From patchwork Wed Mar 15 07:26:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "yong.mao@mediatek.com" X-Patchwork-Id: 739038 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vjjsC3GsHz9ryv for ; Wed, 15 Mar 2017 18:29:03 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751884AbdCOH22 (ORCPT ); Wed, 15 Mar 2017 03:28:28 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:8558 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751549AbdCOH11 (ORCPT ); Wed, 15 Mar 2017 03:27:27 -0400 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1223715725; Wed, 15 Mar 2017 15:26:57 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Wed, 15 Mar 2017 15:26:56 +0800 From: Yong Mao To: Ulf Hansson , Rob Herring CC: Linus Walleij , Daniel Kurtz , Chaotian Jing , yong mao , Eddie Huang , , , , , , Subject: [PATCH v5 1/3] mmc: dt-bindings: update Mediatek MMC bindings Date: Wed, 15 Mar 2017 15:26:38 +0800 Message-ID: <1489562800-27431-2-git-send-email-yong.mao@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1489562800-27431-1-git-send-email-yong.mao@mediatek.com> References: <1489562800-27431-1-git-send-email-yong.mao@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: yong mao Add description for mediatek,hs200-cmd-int-delay Add description for mediatek,hs400-cmd-int-delay Add description for mediatek,hs400-cmd-resp-sel-rising Signed-off-by: Yong Mao Acked-by: Rob Herring --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 0120c7f..4182ea3 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -21,6 +21,15 @@ Optional properties: - assigned-clocks: PLL of the source clock - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock - hs400-ds-delay: HS400 DS delay setting +- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting. + This field has total 32 stages. + The value is an integer from 0 to 31. +- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting + This field has total 32 stages. + The value is an integer from 0 to 31. +- mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection + If present,HS400 command responses are sampled on rising edges. + If not present,HS400 command responses are sampled on falling edges. Examples: mmc0: mmc@11230000 { @@ -38,4 +47,7 @@ mmc0: mmc@11230000 { assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; hs400-ds-delay = <0x14015>; + mediatek,hs200-cmd-int-delay = <26>; + mediatek,hs400-cmd-int-delay = <14>; + mediatek,hs400-cmd-resp-sel-rising; };