pinctrl: qcom: Don't clear status bit on irq_unmask

Submitted by Bjorn Andersson on March 14, 2017, 3:23 p.m.

Details

Message ID 20170314152326.9424-1-bjorn.andersson@linaro.org
State New
Headers show

Commit Message

Bjorn Andersson March 14, 2017, 3:23 p.m.
Clearing the status bit on irq_unmask will discard any pending interrupt
that did arrive after the irq_ack, i.e. while the IRQ handler function
was executing.

Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver")
Cc: stable@vger.kernel.org
Cc: Stephen Boyd <sboyd@codeaurora.org>
Reported-by: Timur Tabi <timur@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 4 ----
 1 file changed, 4 deletions(-)

Comments

Linus Walleij March 16, 2017, 3:32 p.m.
On Tue, Mar 14, 2017 at 4:23 PM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:

> Clearing the status bit on irq_unmask will discard any pending interrupt
> that did arrive after the irq_ack, i.e. while the IRQ handler function
> was executing.
>
> Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver")
> Cc: stable@vger.kernel.org
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Reported-by: Timur Tabi <timur@codeaurora.org>
> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

Patch applied for fixes.

Yours,
Linus Walleij
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Patch hide | download patch | download mbox

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index f8e9e1c2b2f6..faf038978650 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -594,10 +594,6 @@  static void msm_gpio_irq_unmask(struct irq_data *d)
 
 	raw_spin_lock_irqsave(&pctrl->lock, flags);
 
-	val = readl(pctrl->regs + g->intr_status_reg);
-	val &= ~BIT(g->intr_status_bit);
-	writel(val, pctrl->regs + g->intr_status_reg);
-
 	val = readl(pctrl->regs + g->intr_cfg_reg);
 	val |= BIT(g->intr_enable_bit);
 	writel(val, pctrl->regs + g->intr_cfg_reg);