From patchwork Tue Mar 14 15:18:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 738765 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vjJLj1p4kz9s3l for ; Wed, 15 Mar 2017 02:19:41 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="PJZxgNL6"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753012AbdCNPTb (ORCPT ); Tue, 14 Mar 2017 11:19:31 -0400 Received: from mail-qk0-f193.google.com ([209.85.220.193]:36667 "EHLO mail-qk0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750815AbdCNPSi (ORCPT ); Tue, 14 Mar 2017 11:18:38 -0400 Received: by mail-qk0-f193.google.com with SMTP id n141so41466554qke.3; Tue, 14 Mar 2017 08:18:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7Ni9RPF2Ti3qLWKEcUnTzUh+tKNTh+ak2vUgmCs3poY=; b=PJZxgNL6SIm3di80TX35HSiVrRqBMbe0BndWRR69bE3IojdBLP9ns3/DTcgLJJjtMl 5gXLArizh1QvoNUedW0UxV8aSzuESyR8bTUN5uDbfQjsvh93U8lJzywEdBI7M+YWBWUy Y6gqVL7slQ9mT9war1YdhTxhVaYw6YZ/6K7szLR7tRQZfM67bKNpv8RteL45GSWXEa+E VWgVEa8ifEasTxBN3vzv9ak7ybqTKB9vaq0sctfLfYg9mO9vXnmFlSQkOIKtSk7nrIqy +pcc1d4OFdiWPqBZHlggWtPOnhenpXfu080VG5JbG11YLh/G4iSx4PfEe6ItwMjQhFr3 5dmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7Ni9RPF2Ti3qLWKEcUnTzUh+tKNTh+ak2vUgmCs3poY=; b=jxrZ9ABOmdNQn4meUH0+wpYiREwWFXp9MrrE3Njl1M8aP+t6bDw39sAlS6o7cltoK/ g+R4yd9BAlAWIjLgecO50SUibuw3eJrwp3+1PXAjgAxDW7+yhpLdAbkfX7BOfsm/s9bX NU9kBGV447CmPyZovI+KBLgBX43F5CPM3KoPfnD3lbCii0fmAkQMThmts1OrnT8E/li+ SH53gv8HZpsXwCeXTh+lsD5ou2xBt544jHLbEx06WE5cHCwogNejPX7UAKOEQECbhGYF gHPr/z7iqCslOcIgWfEOer9IuZzJBtCjpkeMWmmTjD7amRUghdkih40NNZ7Szxcga1u8 KsIg== X-Gm-Message-State: AFeK/H2KDUmdO+cOm608ivylZP/8bjUBZMB9KGlEz8yWHFqjUqCozUSfc44wLtbV2NvRgQ== X-Received: by 10.55.7.7 with SMTP id 7mr41161336qkh.228.1489504716408; Tue, 14 Mar 2017 08:18:36 -0700 (PDT) Received: from localhost ([2601:184:4780:aac0:25f8:dd96:a084:785a]) by smtp.gmail.com with ESMTPSA id m78sm14584339qki.44.2017.03.14.08.18.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 14 Mar 2017 08:18:35 -0700 (PDT) From: Rob Clark To: iommu@lists.linux-foundation.org Cc: linux-arm-msm@vger.kernel.org, Robin Murphy , Will Deacon , Sricharan , Mark Rutland , Stanimir Varbanov , Rob Clark , devicetree@vger.kernel.org Subject: [PATCH 3/9] Docs: dt: document qcom iommu bindings Date: Tue, 14 Mar 2017 11:18:05 -0400 Message-Id: <20170314151811.17234-4-robdclark@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170314151811.17234-1-robdclark@gmail.com> References: <20170314151811.17234-1-robdclark@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Rob Clark --- .../devicetree/bindings/iommu/qcom,iommu.txt | 113 +++++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/qcom,iommu.txt diff --git a/Documentation/devicetree/bindings/iommu/qcom,iommu.txt b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt new file mode 100644 index 0000000..fd5b7fa --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/qcom,iommu.txt @@ -0,0 +1,113 @@ +* QCOM IOMMU v1 Implementation + +Qualcomm "B" family devices which are not compatible with arm-smmu have +a similar looking IOMMU but without access to the global register space, +and optionally requiring additional configuration to route context irqs +to non-secure vs secure interrupt line. + +** Required properties: + +- compatible : Should be one of: + + "qcom,msm8916-iommu" + +- clock-names : Should be a pair of "iface" (required for IOMMUs + register group access) and "bus" (required for + the IOMMUs underlying bus access). +- clocks : Phandles for respective clocks described by + clock-names. +- #address-cells : must be 1. +- #size-cells : must be 1. +- #iommu-cells : Must be 1. +- ranges : Base address and size of the iommu context banks. +- qcom,iommu-secure-id : secure-id. + +- List of sub-nodes, one per translation context bank. Each sub-node + has the following required properties: + + - compatible : Should be one of: + - "qcom,msm-iommu-v1-ns" : non-secure context bank + - "qcom,msm-iommu-v1-sec" : secure context bank + - reg : Base address and size of context bank within the iommu + - interrupts : The context fault irq. + +** Optional properties: + +- reg : Base address and size of the SMMU local base, should + be only specified if the iommu requires configuration + for routing of context bank irq's to secure vs non- + secure lines. (Ie. if the iommu contains secure + context banks) + + +** Examples: + + apps_iommu: iommu@1e20000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1e20000 0x40000>; + reg = <0x1ef0000 0x3000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_APSS_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <17>; + + // mdp_0: + iommu-ctx@4000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x4000 0x1000>; + interrupts = ; + }; + + // venus_ns: + iommu-ctx@5000 { + compatible = "qcom,msm-iommu-v1-sec"; + reg = <0x5000 0x1000>; + interrupts = ; + }; + }; + + gpu_iommu: iommu@1f08000 { + #address-cells = <1>; + #size-cells = <1>; + #iommu-cells = <1>; + compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; + ranges = <0 0x1f08000 0x10000>; + clocks = <&gcc GCC_SMMU_CFG_CLK>, + <&gcc GCC_GFX_TCU_CLK>; + clock-names = "iface", "bus"; + qcom,iommu-secure-id = <18>; + + // gfx3d_user: + iommu-ctx@1f09000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x1000 0x1000>; + interrupts = ; + }; + + // gfx3d_priv: + iommu-ctx@1f0a000 { + compatible = "qcom,msm-iommu-v1-ns"; + reg = <0x2000 0x1000>; + interrupts = ; + }; + }; + + ... + + venus: video-codec@1d00000 { + ... + iommus = <&apps_iommu 5>; + }; + + mdp: mdp@1a01000 { + ... + iommus = <&apps_iommu 4>; + }; + + gpu@01c00000 { + ... + iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; + };