Patchwork [U-Boot,5/8,v2] P1021MDS: add P1021MDS board support

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Submitter Haiying Wang
Date Dec. 1, 2010, 3:48 p.m.
Message ID <1291218523-4253-1-git-send-email-Haiying.Wang@freescale.com>
Download mbox | patch
Permalink /patch/73839/
State Superseded
Delegated to: Kumar Gala
Headers show

Comments

Haiying Wang - Dec. 1, 2010, 3:48 p.m.
From: Haiying Wang <Haiying.Wang@freescale.com>

Support P1021MDS board to boot from NAND flash (No NOR flash on this
board). And because P1021 only has 256K L2 SRAM, which can not used for final
uboot image, this patch also enables the TPL BOOT on P1021MDS so that DDR can
be initialized in L2 SRAM through SPD code. So there are three stage uboot
images:
* nand_spl, pad from 4KB size to 16KB, load tpl_boot from offset 16KB in NAND.
* tpl_boot, 112KB size. The env variables are copied to offset 128KB
  in L2 SRAM, so that ddr spd code can get the interleaving mode setting in env.
  It loads final uboot image from offset 128KB in NAND.
* final uboot image, size is variable depends on the functions enabled.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Mohit Kumar <Mohit.Kumar@freescale.com>
Signed-off-by: Yu.Liu <Yu.Liu@freescale.com>

---
Changes made based on 2010.12-rc2 release and changes to use objs instead of 
libs. 
 MAINTAINERS                                   |    4 +
 board/freescale/p1021mds/Makefile             |   53 +++
 board/freescale/p1021mds/config.mk            |   31 ++
 board/freescale/p1021mds/ddr.c                |  162 +++++++
 board/freescale/p1021mds/law.c                |   38 ++
 board/freescale/p1021mds/p1021mds.c           |  132 ++++++
 board/freescale/p1021mds/pci.c                |  105 +++++
 board/freescale/p1021mds/tlb.c                |  102 +++++
 boards.cfg                                    |    1 +
 include/configs/P1021MDS.h                    |  568 +++++++++++++++++++++++++
 nand_spl/board/freescale/p1021mds/Makefile    |  135 ++++++
 nand_spl/board/freescale/p1021mds/nand_boot.c |   69 +++
 nand_spl/nand_boot_fsl_elbc.c                 |    6 +-
 tpl/board/freescale/p1021mds/Makefile         |  249 +++++++++++
 tpl/board/freescale/p1021mds/tpl_boot.c       |   80 ++++
 15 files changed, 1734 insertions(+), 1 deletions(-)
 create mode 100644 board/freescale/p1021mds/Makefile
 create mode 100644 board/freescale/p1021mds/config.mk
 create mode 100644 board/freescale/p1021mds/ddr.c
 create mode 100644 board/freescale/p1021mds/law.c
 create mode 100644 board/freescale/p1021mds/p1021mds.c
 create mode 100644 board/freescale/p1021mds/pci.c
 create mode 100644 board/freescale/p1021mds/tlb.c
 create mode 100644 include/configs/P1021MDS.h
 create mode 100644 nand_spl/board/freescale/p1021mds/Makefile
 create mode 100644 nand_spl/board/freescale/p1021mds/nand_boot.c
 create mode 100644 tpl/board/freescale/p1021mds/Makefile
 create mode 100644 tpl/board/freescale/p1021mds/tpl_boot.c

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index f47fca5..350cd3a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17,6 +17,10 @@ 
 #	Board		CPU						#
 #########################################################################
 
+Haiying Wang <Haiying.Wang@freescale.com>
+
+	P1021MDS	P1021
+
 Poonam Aggrwal <poonam.aggrwal@freescale.com>
 
 	P2020RDB	P2020
diff --git a/board/freescale/p1021mds/Makefile b/board/freescale/p1021mds/Makefile
new file mode 100644
index 0000000..da3b87b
--- /dev/null
+++ b/board/freescale/p1021mds/Makefile
@@ -0,0 +1,53 @@ 
+#
+# Copyright (C) 2010 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+COBJS-y	+= pci.o
+COBJS-y	+= ddr.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/p1021mds/config.mk b/board/freescale/p1021mds/config.mk
new file mode 100644
index 0000000..ce903f6
--- /dev/null
+++ b/board/freescale/p1021mds/config.mk
@@ -0,0 +1,31 @@ 
+#
+# Copyright (C) 2010 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or modify it
+# under the terms of the GNU General Public License as published by the Free
+# Software Foundation; either version 2 of the License, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+# p1021mds board
+#
+
+ifndef NAND_SPL
+ifndef TPL_BOOT
+ifeq ($(CONFIG_NAND), y)
+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds
+endif
+endif
+endif
diff --git a/board/freescale/p1021mds/ddr.c b/board/freescale/p1021mds/ddr.c
new file mode 100644
index 0000000..3f08f74
--- /dev/null
+++ b/board/freescale/p1021mds/ddr.c
@@ -0,0 +1,162 @@ 
+/*
+ * Copyright 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned int fsl_ddr_get_mem_data_rate(void)
+{
+	return get_ddr_freq(0);
+}
+
+void fsl_ddr_get_spd(ddr3_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num)
+{
+	int ret;
+
+	/*
+	 * The P1021 only has one DDR controller, and the P1021MDS board has
+	 * only one DIMM slot.
+	 */
+
+	ret = i2c_read(SPD_EEPROM_ADDRESS1, 0, 1, (u8 *)ctrl_dimms_spd,
+			sizeof(ddr3_spd_eeprom_t));
+
+	if (ret) {
+		debug("DDR: failed to read SPD from address %u\n",
+			SPD_EEPROM_ADDRESS1);
+		memset(ctrl_dimms_spd, 0, sizeof(ddr3_spd_eeprom_t));
+	}
+}
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	/*
+	 * Factors to consider for clock adjust:
+	 */
+	popts->clk_adjust = 6;
+
+	/*
+	 * Factors to consider for CPO:
+	 */
+	popts->cpo_override = 0x1f;
+
+	/*
+	 * Factors to consider for write data delay:
+	 */
+	popts->write_data_delay = 2;
+
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 */
+	popts->half_strength_driver_enable = 1;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 1;
+	popts->rtt_override_value = DDR3_RTT_40_OHM; /* 40 Ohm rtt */
+	popts->rtt_wr_override_value = 2; /* Rtt_WR */
+
+	/* Write leveling override */
+	popts->wrlvl_en = 1;
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xa;
+	popts->wrlvl_start = 0x8;
+	/*
+	 * P1021 supports max 32-bit DDR width
+	 */
+	popts->data_bus_width = 1;
+
+	/*
+	 * disable on-the-fly burst chop mode for 32 bit data bus
+	 */
+	popts->OTF_burst_chop_en = 0;
+
+	/*
+	 * Set fixed 8 beat burst for 32 bit data bus
+	 */
+	popts->burst_length = DDR_BL8;
+}
+
+phys_size_t fixed_sdram(void)
+{
+	ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+	u32 temp_sdram_cfg;
+
+	set_next_law(0 , LAW_SIZE_512M , LAW_TRGT_IF_DDR_1);
+
+	out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
+	out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
+	out_be32(&ddr->cs0_config_2, CONFIG_SYS_DDR_CS0_CONFIG_2);
+	out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
+	out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
+	out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
+	out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
+	out_be32(&ddr->ddr_cdr1, CONFIG_SYS_DDR_CDR_1);
+	out_be32(&ddr->ddr_cdr2, CONFIG_SYS_DDR_CDR_1);
+	out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
+	out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
+	out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
+	out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
+	out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
+	out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
+	out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
+	out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
+	out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
+	out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
+	out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
+
+	sync();
+	isync();
+
+	udelay(500);
+
+	/* Let the controller go */
+	temp_sdram_cfg = in_be32(&ddr->sdram_cfg);
+	out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
+
+	return 512 * 1024 * 1024;
+}
+
+phys_size_t init_ddr_dram(void)
+{
+	phys_size_t dram_size = 0;
+#ifdef CONFIG_SPD_EEPROM
+	dram_size = fsl_ddr_sdram();
+#else
+	dram_size = fixed_sdram();
+#endif
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("\n    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/p1021mds/law.c b/board/freescale/p1021mds/law.c
new file mode 100644
index 0000000..aa24733
--- /dev/null
+++ b/board/freescale/p1021mds/law.c
@@ -0,0 +1,38 @@ 
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+#ifndef CONFIG_TPL_BOOT
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_BCSR_BASE_PHYS, LAW_SIZE_256K, LAW_TRGT_IF_LBC),
+#endif /* !CONFIG_TPL_BOOT */
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1021mds/p1021mds.c b/board/freescale/p1021mds/p1021mds.c
new file mode 100644
index 0000000..5d981e2
--- /dev/null
+++ b/board/freescale/p1021mds/p1021mds.c
@@ -0,0 +1,132 @@ 
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <asm/processor.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <asm/mp.h>
+#include <i2c.h>
+#include <ioports.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <fsl_esdhc.h>
+#include <tsec.h>
+#include <netdev.h>
+
+int board_early_init_f(void)
+{
+
+	fsl_lbc_t *lbc = LBC_BASE_ADDR;
+
+#ifdef CONFIG_MMC
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	setbits_be32(&gur->pmuxcr,
+		(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
+#endif
+
+	/* Set ABSWP to implement conversion of addresses in the LBC */
+	setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
+
+	return 0;
+}
+
+int checkboard(void)
+{
+	printf("Board: P1021 MDS\n");
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	return fsl_ddr_sdram_size();
+}
+
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct tsec_info_struct tsec_info[3];
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+
+#ifdef CONFIG_TSEC3
+	SET_STD_TSEC_INFO(tsec_info[num], 3);
+	if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII3_DIS))
+		tsec_info[num].flags |= TSEC_SGMII;
+	num++;
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+		return 0;
+	}
+
+	tsec_eth_init(bis, tsec_info, num);
+
+	return pci_eth_init(bis);
+}
+#endif
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+extern void ft_pci_board_setup(void *blob);
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, base, size);
+
+	ft_pci_board_setup(blob);
+
+}
+#endif
+;
+#ifdef CONFIG_MP
+extern void cpu_mp_lmb_reserve(struct lmb *lmb);
+
+void board_lmb_reserve(struct lmb *lmb)
+{
+	cpu_mp_lmb_reserve(lmb);
+}
+#endif
diff --git a/board/freescale/p1021mds/pci.c b/board/freescale/p1021mds/pci.c
new file mode 100644
index 0000000..ad00dd7
--- /dev/null
+++ b/board/freescale/p1021mds/pci.c
@@ -0,0 +1,105 @@ 
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <hwconfig.h>
+#include <pci.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_pci.h>
+#include <asm/io.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+
+#ifdef CONFIG_PCIE1
+static struct pci_controller pcie1_hose;
+#endif  /* CONFIG_PCIE1 */
+#ifdef CONFIG_PCIE2
+static struct pci_controller pcie2_hose;
+#endif  /* CONFIG_PCIE2 */
+
+void pci_init_board(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	struct fsl_pci_info pci_info[2];
+	u32 devdisr, pordevsr, io_sel;
+	int first_free_busno = 0;
+	int num = 0;
+
+	int pcie_ep, pcie_configured;
+
+	devdisr = in_be32(&gur->devdisr);
+	pordevsr = in_be32(&gur->pordevsr);
+	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
+
+	debug("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
+
+	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
+		printf("    eTSEC2 is in sgmii mode.\n");
+	if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
+		printf("    eTSEC3 is in sgmii mode.\n");
+
+	puts("\n");
+#ifdef CONFIG_PCIE1
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
+		SET_STD_PCIE_INFO(pci_info[num], 1);
+		pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
+		printf("    PCIE1 connected to Slot as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+				&pcie1_hose, first_free_busno);
+	} else {
+		printf("    PCIE1: disabled\n");
+	}
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
+#endif /* CONFIG_PCIE1 */
+
+#ifdef CONFIG_PCIE2
+	pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
+
+	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
+		SET_STD_PCIE_INFO(pci_info[num], 2);
+		pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
+		printf("    PCIE2 connected to Slot as %s (base addr %lx)\n",
+				pcie_ep ? "End Point" : "Root Complex",
+				pci_info[num].regs);
+		first_free_busno = fsl_pci_init_port(&pci_info[num++],
+				&pcie2_hose, first_free_busno);
+
+	} else {
+		printf("    PCIE2: disabled\n");
+	}
+	puts("\n");
+#else
+	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
+#endif /* CONFIG_PCIE2 */
+}
+
+void ft_pci_board_setup(void *blob)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/p1021mds/tlb.c b/board/freescale/p1021mds/tlb.c
new file mode 100644
index 0000000..4619495
--- /dev/null
+++ b/board/freescale/p1021mds/tlb.c
@@ -0,0 +1,102 @@ 
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_1M, 1),
+
+#ifndef CONFIG_TPL_BOOT
+	/* *I*G* - PCIE */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE2_MEM_VIRT + 0x10000000),
+		      (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000),
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE2_MEM_VIRT + 0x10000000),
+		      (CONFIG_SYS_PCIE2_MEM_PHYS + 0x10000000),
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 5, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCIE I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_IO_VIRT, CONFIG_SYS_PCIE2_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_256K, 1),
+
+	/*
+	 * *I*G BCSR/PMC0/PMC1
+	*/
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 7, BOOKE_PAGESZ_256K, 1),
+#endif /* !CONFIG_TPL_BOOT */
+
+	/* *I*G - NAND */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 8, BOOKE_PAGESZ_1M, 1),
+
+#if defined(CONFIG_NAND_SPL) || defined(CONFIG_TPL_BOOT)
+	/* *I*G - L2SRAM */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
+			0, 9, BOOKE_PAGESZ_256K, 1)
+#endif
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 2209676..5c5c7fe 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -480,6 +480,7 @@  P1020RDB                     powerpc     mpc85xx     p1_p2_rdb           freesca
 P1020RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,NAND
 P1020RDB_SDCARD              powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020RDB,SDCARD
 P1020RDB_SPIFLASH            powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P1020,SPIFLASH
+P1021MDS_NAND		     powerpc     mpc85xx     p1021mds            freescale      -           P1021MDS:NAND
 P1022DS                      powerpc     mpc85xx     p1022ds             freescale
 P2010RDB                     powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010
 P2010RDB_NAND                powerpc     mpc85xx     p1_p2_rdb           freescale      -           P1_P2_RDB:P2010,NAND
diff --git a/include/configs/P1021MDS.h b/include/configs/P1021MDS.h
new file mode 100644
index 0000000..2e3d893
--- /dev/null
+++ b/include/configs/P1021MDS.h
@@ -0,0 +1,568 @@ 
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * p1021mds board configuration file
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_TPL_U_BOOT
+
+#ifdef CONFIG_NAND
+#define CONFIG_NAND_U_BOOT
+#define CONFIG_RAMBOOT_NAND
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
+#elif CONFIG_TPL_BOOT
+#define CONFIG_SYS_TEXT_BASE_TPL	0xf8f81000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_TPL /* start of monitor */
+#else
+#define CONFIG_SYS_TEXT_BASE	0x01001000
+#endif
+#endif
+
+#ifndef CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE			/* BOOKE */
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_MPC85xx			/* MPC8540/60/55/41/48/68/P1021 */
+#define CONFIG_P1021			/* P1021 silicon support */
+#define CONFIG_P1021MDS			/* P1021MDS board specific */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+#define CONFIG_FSL_ELBC			/* Has Enhance localbus controller */
+
+/* Replace a call to get_clock_freq (after it is implemented)*/
+#define CONFIG_SYS_CLK_FREQ	66666666
+#define CONFIG_DDR_CLK_FREQ	CONFIG_SYS_CLK_FREQ
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_L2_CACHE				/* toggle L2 cache	*/
+#define CONFIG_BTB				/* toggle branch predition */
+
+#define CONFIG_HWCONFIG
+
+
+/*
+ * Only possible on E500 Version 2 or newer cores.
+ */
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x1fffffff
+
+#define CONFIG_SYS_LBC_LBCR	0x00080000	/* Implement conversion of
+						addresses in the LBC */
+
+/*
+ * Base addresses -- Note these are effective addresses where the
+ * actual resources get mapped (not physical addresses)
+ */
+#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
+#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR
+						/* physical addr of CCSRBAR */
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT	CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
+#endif
+#define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR
+						/* PQII uses CONFIG_SYS_IMMR */
+
+/* DDR Setup */
+#define CONFIG_FSL_DDR3
+#define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for DDR setup*/
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_TLB_START	11
+
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+					/* DDR is system memory*/
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	2
+
+/* I2C addresses of SPD EEPROMs */
+#define SPD_EEPROM_ADDRESS1    0x51    /* CTLR 0 DIMM 0 */
+
+/* These are used when DDR doesn't use SPD.  */
+#define CONFIG_SYS_SDRAM_SIZE           512		/* DDR is 512MB */
+#define CONFIG_SYS_DDR_CS0_BNDS         0x0000001F
+#define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
+#define CONFIG_SYS_DDR_CS0_CONFIG_2	0x00000000
+#define CONFIG_SYS_DDR_SDRAM_CFG	0x47000000
+#define CONFIG_SYS_DDR_SDRAM_CFG_2	0x04401040
+#define CONFIG_SYS_DDR_ZQ_CNTL		0x89080600
+#define CONFIG_SYS_DDR_WRLVL_CNTL	0x86559608
+#define CONFIG_SYS_DDR_CDR_1		0x000eaa00
+#define CONFIG_SYS_DDR_CDR_2		0x00000000
+#define CONFIG_SYS_DDR_OCD_CTRL         0x00000000
+#define CONFIG_SYS_DDR_OCD_STATUS       0x00000000
+#define CONFIG_SYS_DDR_CONTROL          0x470c0000      /* Type = DDR3 */
+#define CONFIG_SYS_DDR_CONTROL_2	0x04401050
+#define CONFIG_SYS_DDR_DATA_INIT        0x1021babe
+#define CONFIG_SYS_DDR_TIMING_3		0x00010000
+#define CONFIG_SYS_DDR_TIMING_0		0x00330004
+#define CONFIG_SYS_DDR_TIMING_1		0x5d5bd746
+#define CONFIG_SYS_DDR_TIMING_2		0x0fa8c8cd
+#define CONFIG_SYS_DDR_SDRAM_MODE	0x40461320
+#define CONFIG_SYS_DDR_SDRAM_MODE_2	0x8000C000
+#define CONFIG_SYS_DDR_SDRAM_INTERVAL	0x0a280000
+#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
+#define CONFIG_SYS_DDR_TIMING_4		0x00220001
+#define CONFIG_SYS_DDR_TIMING_5		0x03402400
+
+#define CONFIG_SYS_DDR_ERR_INT_EN       0x0000000d
+#define CONFIG_SYS_DDR_ERR_DIS          0x00000000
+#define CONFIG_SYS_DDR_SBE              0x00010000
+
+#undef CONFIG_CLOCKS_IN_MHZ
+
+/*
+ * Config the L2 Cache as L2 SRAM
+ */
+#define CONFIG_SYS_INIT_L2_ADDR         0xf8f80000
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS    CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_L2_SIZE              (256 << 10)
+#define CONFIG_SYS_INIT_L2_END  (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
+
+
+/*
+ * Memory map
+ *
+ * 0x0000_0000 0x1fff_ffff	DDR3			512MB cacheable
+ * 0xa000_0000 0xbfff_ffff	PCIE2 Mem		512MB non-cacheable
+ * 0xc000_0000 0xdfff_ffff	PCIE1 Mem		512MB non-cacheable
+ * 0xffc1_0000 0xffc1_ffff	PCIE2 IO range		64K non-cacheable
+ * 0xffc2_0000 0xffc2_ffff	PCIE1 IO range		64K non-cacheable
+ * 0xf800_0000 0xf800_7fff	BCSR on CS1		32KB non-cacheable
+ * 0xf801_0000 0xf801_ffff	PMC1 on CS2		64KB non-cacheable
+ * 0xf802_0000 0xf802_ffff	PMC0 on CS3		64KB non-cacheable
+ * 0xfc00_0000 0xfdff_ffff	NAND on CS0		32MB non-cacheable
+ * 0xffe0_0000 0xffef_ffff	CCSRBAR			1M
+ */
+
+
+/*
+ * Local Bus Definitions
+ */
+
+#define CONFIG_SYS_BCSR_BASE		0xf8000000
+#define CONFIG_SYS_BCSR_BASE_PHYS	CONFIG_SYS_BCSR_BASE
+
+#define CONFIG_SYS_PIB_PMC1_BASE	0xf8010000
+					/* start of PIB-QOC3(PMC1)  64K */
+#define CONFIG_SYS_PIB_PMC1_BASE_PHYS	CONFIG_SYS_PIB_PMC1_BASE
+
+#define CONFIG_SYS_PIB_PMC0_BASE	0xf8020000
+					/* start of PIB-T1/E1(PMC0) 64K */
+#define CONFIG_SYS_PIB_PMC0_BASE_PHYS	CONFIG_SYS_PIB_PMC0_BASE
+
+/* chip select 1 - BCSR*/
+#define CONFIG_SYS_BR1_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
+				| BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM  (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+				| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+
+/* chip select 2 - PIB(QOC3-PMC1)*/
+#define CONFIG_SYS_BR2_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_PIB_PMC1_BASE_PHYS) \
+				| BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR2_PRELIM  (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+				| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+
+/* chip select 3 - PIB(T1/E1-PMC0)*/
+#define CONFIG_SYS_BR3_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_PIB_PMC0_BASE_PHYS) \
+				| BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM  (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS \
+				| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
+				| OR_GPCM_EAD)
+
+#define CONFIG_SYS_NO_FLASH
+
+#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) \
+		 || defined(CONFIG_RAMBOOT_SPIFLASH)
+#define CONFIG_SYS_RAMBOOT
+#else
+#undef CONFIG_SYS_RAMBOOT
+#endif
+
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_BASE		0xFFF00000
+#else
+#define CONFIG_SYS_NAND_BASE		0xFC000000
+#endif
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE, }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define NAND_MAX_CHIPS			1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+#define CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(16 * 1024)
+
+/* NAND boot: 4K NAND loader config */
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_SYS_NAND_SPL_SIZE	0x1000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(112 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_INIT_L2_ADDR
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(16 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC    (CONFIG_SYS_INIT_L2_END - 0x2000)
+#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
+#endif
+#ifdef CONFIG_TPL_BOOT
+/* tpl boot: 112K  tpl uboot config*/
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	(512 << 10)
+#define CONFIG_SYS_NAND_U_BOOT_DST	(0x01000000)
+#define CONFIG_SYS_NAND_U_BOOT_START	(0x01000000)
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	(128 << 10)
+#endif
+
+/* NAND FLASH CONFIG */
+#define CONFIG_NAND_BR_PRELIM	(CONFIG_SYS_NAND_BASE_PHYS \
+				| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+				| BR_PS_8	     /* Port Size = 8 bit */ \
+				| BR_MS_FCM	     /* MSEL = FCM */ \
+				| BR_V)		     /* valid */
+#define CONFIG_NAND_OR_PRELIM	(0xFFF80000	     /* length 32K */ \
+				| OR_FCM_CSCT \
+				| OR_FCM_CST \
+				| OR_FCM_CHT \
+				| OR_FCM_SCY_1 \
+				| OR_FCM_TRLX \
+				| OR_FCM_EHTR)
+/* chip select 0 - NAND */
+#define CONFIG_SYS_BR0_PRELIM	CONFIG_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM	CONFIG_NAND_OR_PRELIM /* NAND Options */
+
+#define CONFIG_SYS_INIT_RAM_LOCK	1
+#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial RAM address */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* End of used area in RAM */
+
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* num bytes initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	\
+			(CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
+
+/* Serial Port */
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SERIAL_MULTI
+#undef	CONFIG_SERIAL_SOFTWARE_FIFO
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE    1
+#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV   /* determine from environment */
+
+#define CONFIG_SYS_BAUDRATE_TABLE  \
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)
+#ifdef CONFIG_NAND_SPL
+#define CONFIG_NS16550_MIN_FUNCTIONS
+#endif
+
+#define CONFIG_BAUDRATE	115200
+
+/* Use the HUSH parser*/
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/*
+ * I2C
+ */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support*/
+#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
+#define CONFIG_SYS_I2C_SLAVE	0x7F
+#define CONFIG_SYS_I2C_NOPROBES	{{0, 0x69}}	/* Don't probe these addrs */
+#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C2_OFFSET	0x3100
+
+/*
+ * Environment
+ */
+#if defined(CONFIG_NAND)
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET	(576 * 1024)
+#define CONFIG_ENV_SIZE		CONFIG_SYS_NAND_BLOCK_SIZE
+#endif
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_INIT_L2_ADDR + (128 << 10))
+
+#define CONFIG_SYS_HZ	1000		/* decrementer freq: 1ms ticks */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	512		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
+						/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
+						/* Boot Argument Buffer Size */
+
+/*********************************/
+#ifndef CONFIG_TPL_BOOT
+
+#define CONFIG_MP			/* Multiprocessor support */
+
+#define CONFIG_PCI			/* Disable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controller */
+#define CONFIG_PCIE2			/* PCIE controller */
+#define CONFIG_FSL_PCI_INIT		/* use common fsl pci init code */
+#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TSEC_ENET		/* tsec ethernet support */
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+#define CONFIG_SYS_64BIT_STRTOUL
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	 /* enable fit_format_{error,warning}() */
+
+/* TSEC support */
+#if defined(CONFIG_TSEC_ENET)
+
+/* TSECV2 */
+#define CONFIG_TSECV2
+
+#ifndef CONFIG_NET_MULTI
+#define CONFIG_NET_MULTI
+#endif
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
+#define CONFIG_TSEC1
+#define CONFIG_TSEC1_NAME	"eTSEC1"
+#define CONFIG_TSEC2
+#define CONFIG_TSEC2_NAME	"eTSEC2"
+#define CONFIG_TSEC3
+#define CONFIG_TSEC3_NAME	"eTSEC3"
+
+#define TSEC1_PHY_ADDR		0
+#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#define TSEC1_PHYIDX		0
+
+#define TSEC2_PHY_ADDR		4
+#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_SGMII)
+#define TSEC2_PHYIDX		0
+
+#ifdef CONFIG_TSEC3_IN_SGMII	/* Need to set SW8.6 to 0 */
+#define TSEC3_PHY_ADDR		6
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_SGMII)
+#else
+#define TSEC3_PHY_ADDR		1
+#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
+#endif
+#define TSEC3_PHYIDX		0
+
+#define CONFIG_ETHPRIME		"eTSEC1"
+
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif /* CONFIG_TSEC_ENET */
+
+/*
+ * I2C2 EEPROM
+ */
+#define CONFIG_ID_EEPROM
+#ifdef CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#endif
+#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_BUS_NUM       1
+
+#define PLPPAR1_I2C_BIT_MASK		0x0000000F
+#define PLPPAR1_I2C2_VAL		0x00000000
+#define PLPPAR1_ESDHC_VAL		0x0000000A
+#define PLPDIR1_I2C_BIT_MASK		0x0000000F
+#define PLPDIR1_I2C2_VAL		0x0000000F
+#define PLPDIR1_ESDHC_VAL		0x00000006
+
+/*
+ * General PCI
+ * Memory Addresses are mapped 1-1. I/O is mapped from 0
+ */
+#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64K */
+
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64K */
+
+#if defined(CONFIG_PCI)
+#define CONFIG_PCI_PNP                 /* do pci plug-and-play */
+#endif
+
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_SETEXPR
+
+#if defined(CONFIG_PCI)
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#undef CONFIG_WATCHDOG			/* watchdog disabled */
+
+#define CONFIG_BOARD_EARLY_INIT_F	/* Call board_pre_init */
+
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 16 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)
+					/* Initial Memory map for Linux*/
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM	0x02		/* Software reboot */
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_HOSTNAME	p1021mds
+#define CONFIG_ROOTPATH	/nfsroot
+#define CONFIG_BOOTFILE	your.uImage
+
+#define CONFIG_LOADADDR	1000000   /*default location for tftp and bootm*/
+
+#define CONFIG_BOOTDELAY 10       /* -1 disables auto-boot */
+#undef  CONFIG_BOOTARGS           /* the boot command will set bootargs*/
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"consoledev=ttyS0\0"						\
+	"ramdiskaddr=2000000\0"						\
+	"ramdiskfile=your.ramdisk.u-boot\0"				\
+	"fdtaddr=c00000\0"						\
+	"fdtfile=your.fdt.dtb\0"					\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+	"nfsroot=$serverip:$rootpath "					\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw "			\
+	"console=$consoledev,$baudrate $othbootargs\0"			\
+
+#define CONFIG_NFSBOOTCOMMAND						\
+	"run nfsargs;"							\
+	"tftp $loadaddr $bootfile;"					\
+	"tftp $fdtaddr $fdtfile;"					\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND						\
+	"run ramargs;"							\
+	"tftp $ramdiskaddr $ramdiskfile;"				\
+	"tftp $loadaddr $bootfile;"					\
+	"bootm $loadaddr $ramdiskaddr"
+
+#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND
+
+#endif /* !CONFIG_TPL_BOOT */
+#endif	/* __CONFIG_H */
diff --git a/nand_spl/board/freescale/p1021mds/Makefile b/nand_spl/board/freescale/p1021mds/Makefile
new file mode 100644
index 0000000..dfea761
--- /dev/null
+++ b/nand_spl/board/freescale/p1021mds/Makefile
@@ -0,0 +1,135 @@ 
+#
+# Copyright (C) 2010 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+NAND_SPL := y
+CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
+PAD_TO := 0xfff04000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
+		$(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_NAND_SPL
+CFLAGS	+= -DCONFIG_NAND_SPL
+
+SOBJS	= start.o resetvec.o
+COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
+	  nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
+
+nandobj	:= $(OBJTREE)/nand_spl/
+
+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
+
+all:	$(obj).depend $(ALL)
+
+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
+
+$(nandobj)u-boot-spl:	$(OBJS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
+		-Map $(nandobj)u-boot-spl.map \
+		-o $(nandobj)u-boot-spl
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+	@rm -f $(obj)cache.c
+	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+	@rm -f $(obj)cpu_init_early.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c \
+	 $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+	@rm -f $(obj)cpu_init_nand.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c \
+	$(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+	@rm -f $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+	@rm -f $(obj)law.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+	@rm -f $(obj)nand_boot_fsl_elbc.c
+	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+	       $(obj)nand_boot_fsl_elbc.c
+
+$(obj)ns16550.c:
+	@rm -f $(obj)ns16550.c
+	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)resetvec.S:
+	@rm -f $(obj)resetvec.S
+	ln -s $(SRCTREE)/arch/powerpc/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
+
+$(obj)fixed_ivor.S:
+	@rm -f $(obj)fixed_ivor.S
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/fixed_ivor.S \
+	$(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+	@rm -f $(obj)start.S
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/start.S $(obj)start.S
+
+$(obj)tlb.c:
+	@rm -f $(obj)tlb.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+	@rm -f $(obj)tlb_table.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)nand_boot.c:
+	@rm -f $(obj)nand_boot.c
+	ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c \
+	 $(obj)nand_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/nand_spl/board/freescale/p1021mds/nand_boot.c b/nand_spl/board/freescale/p1021mds/nand_boot.c
new file mode 100644
index 0000000..f0f2063
--- /dev/null
+++ b/nand_spl/board/freescale/p1021mds/nand_boot.c
@@ -0,0 +1,69 @@ 
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void board_init_f(ulong bootflag)
+{
+	uint plat_ratio, bus_clk, sys_clk = 0;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	sys_clk = CONFIG_SYS_CLK_FREQ;
+
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = plat_ratio * sys_clk;
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+			bus_clk / 16 / CONFIG_BAUDRATE);
+
+	puts("\nNAND boot... ");
+	/* copy code to DDR and jump to it - this should not return */
+	/* NOTE - code has to be copied out of NAND buffer before
+	 * other blocks can be read.
+	 */
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
+			CONFIG_SYS_NAND_U_BOOT_RELOC);
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+	nand_boot();
+}
+
+void putc(char c)
+{
+	if (c == '\n')
+		NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
+
+	NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
+}
+
+void puts(const char *str)
+{
+	while (*str)
+		putc(*str++);
+}
diff --git a/nand_spl/nand_boot_fsl_elbc.c b/nand_spl/nand_boot_fsl_elbc.c
index 9547d44..7bd84ce 100644
--- a/nand_spl/nand_boot_fsl_elbc.c
+++ b/nand_spl/nand_boot_fsl_elbc.c
@@ -4,7 +4,7 @@ 
  * (C) Copyright 2006-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * Copyright (c) 2008 Freescale Semiconductor, Inc.
+ * Copyright (c) 2008-2010 Freescale Semiconductor, Inc.
  * Author: Scott Wood <scottwood@freescale.com>
  *
  * This program is free software; you can redistribute it and/or
@@ -47,7 +47,11 @@  static void nand_wait(void)
 	}
 }
 
+#ifdef CONFIG_TPL_BOOT
+void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#else
 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
+#endif
 {
 	fsl_lbc_t *regs = LBC_BASE_ADDR;
 	uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
diff --git a/tpl/board/freescale/p1021mds/Makefile b/tpl/board/freescale/p1021mds/Makefile
new file mode 100644
index 0000000..ffa2e5e
--- /dev/null
+++ b/tpl/board/freescale/p1021mds/Makefile
@@ -0,0 +1,249 @@ 
+#
+# Copyright (C) 2010 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+TPL_BOOT := y
+CONFIG_SYS_TEXT_BASE_TPL := 0xf8f81000
+PAD_TO := 0xf8f9c000
+
+include $(TOPDIR)/config.mk
+
+LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-tpl.lds
+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(CONFIG_SYS_TEXT_BASE_TPL) \
+		 $(PLATFORM_LDFLAGS)
+AFLAGS	+= -DCONFIG_TPL_BOOT
+CFLAGS	+= -DCONFIG_TPL_BOOT
+
+SOBJS	= start.o ticks.o ppcstring.o
+COBJS	= cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o speed.o \
+	  tpl_boot.o tlb.o tlb_table.o ddr-gen3.o ddr.o time.o \
+	  string.o hwconfig.o time_lib.o ddr_spd.o ctype.o div64.o crc32.o\
+	  console.o cmd_nvedit.o env_common.o env_nand.o vsprintf.o \
+	  display_options.o hashtable.o dlmalloc.o stdio.o ns16550.o serial.o \
+	  errno.o command.o serial_driver.o qsort.o
+
+ifdef CONFIG_RAMBOOT_NAND
+COBJS += nand_boot_fsl_elbc.o
+endif
+
+LIBS = $(OBJTREE)/arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
+LIBS += $(OBJTREE)/drivers/i2c/libi2c.o
+
+SRCS	:= $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+__OBJS	:= $(SOBJS) $(COBJS)
+__LIBS	:= $(addprefix $(obj), $(LIBS))
+LNDIR	:= $(OBJTREE)/tpl/board/$(BOARDDIR)
+
+tplobj	:= $(OBJTREE)/tpl/
+
+ALL	= $(tplobj)u-boot-tpl $(tplobj)u-boot-tpl.bin
+
+all:	$(obj).depend $(ALL)
+
+$(tplobj)u-boot-tpl.bin: $(tplobj)u-boot-tpl
+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
+
+$(tplobj)u-boot-tpl:	$(OBJS) $(LIBS)
+	cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(__LIBS) $(PLATFORM_LIBS) \
+		-Map $(tplobj)u-boot-tpl.map \
+		-o $(tplobj)u-boot-tpl
+
+# create symbolic links for common files
+
+$(obj)cache.c:
+	@rm -f $(obj)cache.c
+	ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
+
+$(obj)cpu_init_early.c:
+	@rm -f $(obj)cpu_init_early.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
+
+$(obj)cpu_init_nand.c:
+	@rm -f $(obj)cpu_init_nand.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
+
+$(obj)fsl_law.c:
+	@rm -f $(obj)fsl_law.c
+	ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
+
+$(obj)law.c:
+	@rm -f $(obj)law.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
+
+$(obj)nand_boot_fsl_elbc.c:
+	@rm -f $(obj)nand_boot_fsl_elbc.c
+	ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
+	       $(obj)nand_boot_fsl_elbc.c
+
+$(obj)fixed_ivor.S:
+	@rm -f $(obj)fixed_ivor.S
+	ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
+
+$(obj)start.S: $(obj)fixed_ivor.S
+	@rm -f $(obj)start.S
+	ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
+
+$(obj)speed.c:
+	@rm -f $(obj)speed.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/speed.c $(obj)speed.c
+
+$(obj)interrupts.c:
+	@rm -f $(obj)interrupts.c
+	ln -sf $(SRCTREE)/arch/powerpc/lib/interrupts.c $(obj)interrupts.c
+
+$(obj)ticks.S:
+	@rm -f $(obj)ticks.S
+	ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
+
+$(obj)bootm.c:
+	@rm -f $(obj)bootm.c
+	ln -sf $(SRCTREE)/arch/powerpc/lib/bootm.c $(obj)bootm.c
+
+$(obj)tlb.c:
+	@rm -f $(obj)tlb.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
+
+$(obj)tlb_table.c:
+	@rm -f $(obj)tlb_table.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
+
+$(obj)ddr.c:
+	@rm -f $(obj)ddr.c
+	ln -sf $(SRCTREE)/board/$(BOARDDIR)/ddr.c $(obj)ddr.c
+
+$(obj)time.c:
+	@rm -f $(obj)time.o
+	ln -sf $(SRCTREE)/arch/powerpc/lib/time.c $(obj)time.c
+
+$(obj)ddr-gen3.c:
+	@rm -f $(obj)ddr-gen3.c
+	ln -sf $(SRCTREE)/$(CPUDIR)/ddr-gen3.c $(obj)ddr-gen3.c
+
+$(obj)ppcstring.S:
+	@rm -f $(obj)ppcstring.S
+	ln -sf $(SRCTREE)/arch/powerpc/lib/ppcstring.S $(obj)ppcstring.S
+
+$(obj)ns16550.c:
+	@rm -f $(obj)ns16550.c
+	ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
+
+$(obj)serial_driver.c:
+	@rm -f $(obj)serial_driver.c
+	ln -sf $(SRCTREE)/drivers/serial/serial.c $(obj)serial_driver.c
+
+$(obj)time_lib.c:
+	@rm -f $(obj)time_lib.o
+	ln -sf $(SRCTREE)/lib/time.c $(obj)time_lib.c
+
+$(obj)ddr_spd.c:
+	@rm -f $(obj)ddr_spd.c
+	ln -sf $(SRCTREE)/common/ddr_spd.c $(obj)ddr_spd.c
+
+$(obj)ctype.c:
+	@rm -f $(obj)ctype.c
+	ln -sf $(SRCTREE)/lib/ctype.c $(obj)ctype.c
+
+$(obj)div64.c:
+	@rm -f $(obj)div64.c
+	ln -sf $(SRCTREE)/lib/div64.c $(obj)div64.c
+
+$(obj)crc32.c:
+	@rm -f $(obj)crc32.c
+	ln -sf $(SRCTREE)/lib/crc32.c $(obj)crc32.c
+
+$(obj)env_common.c:
+	@rm -f $(obj)env_common.c
+	ln -sf $(SRCTREE)/common/env_common.c $(obj)env_common.c
+
+$(obj)env_nand.c:
+	@rm -f $(obj)env_nand.c
+	ln -sf $(SRCTREE)/common/env_nand.c $(obj)env_nand.c
+
+$(obj)cmd_nvedit.c:
+	@rm -f $(obj)cmd_nvedit.c
+	ln -sf $(SRCTREE)/common/cmd_nvedit.c $(obj)cmd_nvedit.c
+
+$(obj)console.c:
+	@rm -f $(obj)console.c
+	ln -sf $(SRCTREE)/common/console.c $(obj)console.c
+
+$(obj)dlmalloc.c:
+	@rm -f $(obj)dlmalloc.c
+	ln -sf $(SRCTREE)/common/dlmalloc.c $(obj)dlmalloc.c
+
+$(obj)hwconfig.c:
+	@rm -f $(obj)hwconfig.c
+	ln -sf $(SRCTREE)/common/hwconfig.c $(obj)hwconfig.c
+
+$(obj)stdio.c:
+	@rm -f $(obj)stdio.c
+	ln -sf $(SRCTREE)/common/stdio.c $(obj)stdio.c
+
+$(obj)string.c:
+	@rm -f $(obj)string.c
+	ln -sf $(SRCTREE)/lib/string.c $(obj)string.c
+
+$(obj)vsprintf.c:
+	@rm -f $(obj)vsprintf.c
+	ln -sf $(SRCTREE)/lib/vsprintf.c $(obj)vsprintf.c
+
+$(obj)display_options.c:
+	@rm -f $(obj)display_options.c
+	ln -sf $(SRCTREE)/lib/display_options.c $(obj)display_options.c
+
+$(obj)hashtable.c:
+	@rm -f $(obj)hashtable.c
+	ln -sf $(SRCTREE)/lib/hashtable.c $(obj)hashtable.c
+
+$(obj)serial.c:
+	@rm -f $(obj)serial.c
+	ln -sf $(SRCTREE)/common/serial.c $(obj)serial.c
+
+$(obj)command.c:
+	@rm -f $(obj)command.c
+	ln -sf $(SRCTREE)/common/command.c $(obj)command.c
+
+$(obj)errno.c:
+	@rm -f $(obj)errno.c
+	ln -sf $(SRCTREE)/lib/errno.c $(obj)errno.c
+
+$(obj)qsort.c:
+	@rm -f $(obj)qsort.c
+	ln -sf $(SRCTREE)/lib/qsort.c $(obj)qsort.c
+
+ifneq ($(OBJTREE), $(SRCTREE))
+$(obj)tpl_boot.c:
+	@rm -f $(obj)tpl_boot.c
+	ln -s $(SRCTREE)/tpl/freescale/tpl_boot.c $(obj)tpl_boot.c
+endif
+
+#########################################################################
+
+$(obj)%.o:	$(obj)%.S
+	$(CC) $(AFLAGS) -c -o $@ $<
+
+$(obj)%.o:	$(obj)%.c
+	$(CC) $(CFLAGS) -c -o $@ $<
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/tpl/board/freescale/p1021mds/tpl_boot.c b/tpl/board/freescale/p1021mds/tpl_boot.c
new file mode 100644
index 0000000..47d6568
--- /dev/null
+++ b/tpl/board/freescale/p1021mds/tpl_boot.c
@@ -0,0 +1,80 @@ 
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <mpc85xx.h>
+#include <asm/io.h>
+#include <ns16550.h>
+#include <nand.h>
+#include <asm/mmu.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern void nand_load(unsigned int offs, int uboot_size, uchar *dst);
+extern phys_size_t init_ddr_dram(void);
+ulong load_addr = CONFIG_SYS_LOAD_ADDR;
+
+void board_init_f(ulong bootflag)
+{
+	uint plat_ratio, bus_clk, sys_clk = 0;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+
+	sys_clk = CONFIG_SYS_CLK_FREQ;
+
+	plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
+	plat_ratio >>= 1;
+	bus_clk = plat_ratio * sys_clk;
+	get_clocks();
+
+	NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
+			bus_clk / 16 / CONFIG_BAUDRATE);
+
+	/* load environment */
+#ifdef CONFIG_NAND_U_BOOT
+	nand_load(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
+				(uchar *)CONFIG_ENV_ADDR);
+#endif
+
+	gd->env_addr  = (ulong)(CONFIG_ENV_ADDR);
+	gd->env_valid = 1;
+
+	/* board specific DDR initialization */
+	gd->ram_size = init_ddr_dram();
+	puts("DRAM:");
+	print_size(gd->ram_size, "");
+
+	puts("\nThird program loader running in sram... ");
+
+	/*
+	 * Load final image to DDR and let it run from there.
+	 */
+#ifdef CONFIG_NAND_U_BOOT
+	nand_boot();
+#endif
+}
+
+void board_init_r(gd_t *gd, ulong dest_addr)
+{
+}