From patchwork Mon Mar 13 14:22:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 738183 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vhgDz5C9Mz9s0g for ; Tue, 14 Mar 2017 01:27:31 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="DUJab/hv"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753704AbdCMO12 (ORCPT ); Mon, 13 Mar 2017 10:27:28 -0400 Received: from fllnx209.ext.ti.com ([198.47.19.16]:9525 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753226AbdCMO0E (ORCPT ); Mon, 13 Mar 2017 10:26:04 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllnx209.ext.ti.com (8.15.1/8.15.1) with ESMTP id v2DEO7dG018021; Mon, 13 Mar 2017 09:24:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1489415047; bh=kh8AgjIIboPJREeA7w5kck3ffnLvmB41+G1VHCsu74k=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=DUJab/hvKJkqhyxBwMjlpZBPKWzxcUKNYRMMyuXOdTnmeMSQ6UigCoqiopL5ERqO3 2pVo3tDee6WqDNyiRfOahok7nFgNDj9rVOPrgR0AsFpU6y9gorTbjp7p8KYMsj8HKQ wzqck7j1m6swfojQ0PVskcfqZ42C8J/yIatt59rs= Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DEO2Nn004190; Mon, 13 Mar 2017 09:24:02 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.294.0; Mon, 13 Mar 2017 09:24:01 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v2DEN3eU003368; Mon, 13 Mar 2017 09:23:58 -0500 From: Kishon Vijay Abraham I To: Bjorn Helgaas , Joao Pinto , , , , , , CC: , , Subject: [PATCH v4 14/23] PCI: dwc: dra7xx: Workaround for errata id i870 Date: Mon, 13 Mar 2017 19:52:50 +0530 Message-ID: <20170313142259.25397-15-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170313142259.25397-1-kishon@ti.com> References: <20170313142259.25397-1-kishon@ti.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org According to errata i870, access to the PCIe slave port that are not 32-bit aligned will result in incorrect mapping to TLP Address and Byte enable fields. Accessing non 32-bit aligned data causes incorrect data in the target buffer if memcpy is used. Implement the workaround for this errata here. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/dwc/pci-dra7xx.c | 53 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c index 35c18534469c..147d37a7fe58 100644 --- a/drivers/pci/dwc/pci-dra7xx.c +++ b/drivers/pci/dwc/pci-dra7xx.c @@ -26,6 +26,8 @@ #include #include #include +#include +#include #include "pcie-designware.h" @@ -528,6 +530,51 @@ static const struct of_device_id of_dra7xx_pcie_match[] = { {}, }; +/* + * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870 + * @dra7xx: the dra7xx device where the workaround should be applied + * + * Access to the PCIe slave port that are not 32-bit aligned will result + * in incorrect mapping to TLP Address and Byte enable fields. Therefore, + * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or + * 0x3. + * + * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1. + */ +static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev) +{ + int ret; + struct device_node *np = dev->of_node; + struct regmap *regmap; + unsigned int reg; + unsigned int field; + + regmap = syscon_regmap_lookup_by_phandle(np, + "ti,syscon-unaligned-access"); + if (IS_ERR(regmap)) { + dev_dbg(dev, "can't get ti,syscon-unaligned-access\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 1, + ®)) { + dev_err(dev, "couldn't get legacy mode register offset\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 2, + &field)) { + dev_err(dev, "can't get bit field for setting legacy mode\n"); + return -EINVAL; + } + + ret = regmap_update_bits(regmap, reg, field, field); + if (ret) + dev_err(dev, "failed to enable unaligned access\n"); + + return ret; +} + static int __init dra7xx_pcie_probe(struct platform_device *pdev) { u32 reg; @@ -637,6 +684,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) case DW_PCIE_RC_TYPE: dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_RC); + ret = dra7xx_add_pcie_port(dra7xx, pdev); if (ret < 0) goto err_gpio; @@ -644,6 +692,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev) case DW_PCIE_EP_TYPE: dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE, DEVICE_TYPE_EP); + + ret = dra7xx_pcie_ep_unaligned_memaccess(dev); + if (ret) + goto err_gpio; + ret = dra7xx_add_pcie_ep(dra7xx, pdev); if (ret < 0) goto err_gpio;