[GIT,PULL,00/23] PCI: Support for configurable PCI endpoint

Submitted by Kishon Vijay Abraham I on March 13, 2017, 2:22 p.m.

Details

Message ID 20170313142259.25397-1-kishon@ti.com
State New
Headers show

Pull-request

git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git tags/pci-endpoint-for-4.12

Commit Message

Kishon Vijay Abraham I March 13, 2017, 2:22 p.m.
Please find the pull request for PCI endpoint support below. I've
also included all the history here.

Changes from v3:
*) fixed a typo and adapted to https://lkml.org/lkml/2017/3/13/562.

Changes from v2:
*) changed the configfs structure as suggested by Christoph Hellwig. With
   this change the framework creates configfs entry for EP function driver
   and EP controller. Previously these entries have to be created by the
   the user. (Haven't changed the epc core or epf core except for invoking
   configfs APIs to create entries for EP function driver and EP controller.
   That's mostly because the EP function device can still be created by
   directly invoking the epf core API without using configfs).
*) Now the user has to use configfs entry 'start' to start the link.
   This was previously done by the function driver. However in the case of
   multi function EP, the function driver shouldn't start the link.

Changes from v1:
*) The preparation patches for adding EP support is removed and is sent
   separately
*) Added device ID for DRA74x/DRA72x and used it instead of
   using "PCI_ANY_ID"
*) Added userguide for PCI endpoint test function

Major Improvements from RFC:
 *) support multi-function devices (hw supported not virtual)
 *) Access host side buffers
 *) Raise MSI interrupts
 *) Add user space program to use the host side PCI driver
 *) Adapt all other users of designware to use the new design (only
    compile tested. Since I have only dra7xx boards, the new design
    has only been tested in dra7xx. I'd require the help of others
    to test the platforms they have access to).

This series has been developed over 4.11-rc1 + [1]

[1] -> https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1348667.html

The following changes since commit 29b1586a2e7d564dd801c5792122bdf00fab0cec:

  PCI: dwc: dra7xx: Push request_irq call to the bottom of probe (2017-03-13 19:17:10 +0530)

are available in the git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git tags/pci-endpoint-for-4.12

for you to fetch changes up to 6a02235543fb24f2468cba3b02f75d6c44ff9262:

  ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP (2017-03-13 19:23:04 +0530)

----------------------------------------------------------------
pci: endpoint: for 4.12

 *) Add PCI endpoint core layer
 *) Modify designware and dra7xx driver to be configured in EP mode
 *) Add a PCI endpoint *test* function driver and corresponding host
    driver

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

----------------------------------------------------------------
Kishon Vijay Abraham I (23):
      PCI: endpoint: Add EP core layer to enable EP controller and EP functions
      Documentation: PCI: Guide to use PCI Endpoint Core Layer
      PCI: endpoint: Introduce configfs entry for configuring EP functions
      Documentation: PCI: Guide to use pci endpoint configfs
      PCI: endpoint: Create configfs entry for EPC device and EPF driver
      Documentation: PCI: Add specification for the *pci test* function device
      PCI: endpoint: functions: Add an EP function to test PCI
      Documentation: PCI: Add binding documentation for pci-test endpoint function
      PCI: dwc: designware: Add EP mode support
      dt-bindings: PCI: Add dt bindings for pci designware EP mode
      PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently
      PCI: dwc: dra7xx: Add EP mode support
      dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
      PCI: dwc: dra7xx: Workaround for errata id i870
      dt-bindings: PCI: dra7xx: Add dt bindings to enable unaligned access
      PCI: Add device IDs for DRA74x and DRA72x
      misc: Add host side pci driver for pci test function device
      Documentation: misc-devices: Add Documentation for pci-endpoint-test driver
      tools: PCI: Add a userspace tool to test PCI endpoint
      tools: PCI: Add sample test script to invoke pcitest
      Documentation: PCI: Add userguide for PCI endpoint test function
      MAINTAINERS: add PCI EP maintainer
      ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP

 Documentation/PCI/00-INDEX                                |  10 +++
 Documentation/PCI/endpoint/function/binding/pci-test.txt  |  17 +++++
 Documentation/PCI/endpoint/pci-endpoint-cfs.txt           | 105 ++++++++++++++++++++++++++
 Documentation/PCI/endpoint/pci-endpoint.txt               | 215 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 Documentation/PCI/endpoint/pci-test-function.txt          |  66 ++++++++++++++++
 Documentation/PCI/endpoint/pci-test-howto.txt             | 179 +++++++++++++++++++++++++++++++++++++++++++
 Documentation/devicetree/bindings/pci/designware-pcie.txt |  26 +++++--
 Documentation/devicetree/bindings/pci/ti-pci.txt          |  42 +++++++++--
 Documentation/misc-devices/pci-endpoint-test.txt          |  35 +++++++++
 MAINTAINERS                                               |   9 +++
 arch/arm/mach-omap2/clockdomains7xx_data.c                |   2 +-
 drivers/Makefile                                          |   2 +
 drivers/misc/Kconfig                                      |   7 ++
 drivers/misc/Makefile                                     |   1 +
 drivers/misc/pci_endpoint_test.c                          | 534 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/Kconfig                                       |   1 +
 drivers/pci/dwc/Kconfig                                   |  36 ++++++++-
 drivers/pci/dwc/Makefile                                  |   5 +-
 drivers/pci/dwc/pci-dra7xx.c                              | 274 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----
 drivers/pci/dwc/pcie-designware-ep.c                      | 342 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/dwc/pcie-designware.c                         | 125 ++++++++++++++++++++++++++++++
 drivers/pci/dwc/pcie-designware.h                         | 112 +++++++++++++++++++++++++++
 drivers/pci/endpoint/Kconfig                              |  31 ++++++++
 drivers/pci/endpoint/Makefile                             |   7 ++
 drivers/pci/endpoint/functions/Kconfig                    |  12 +++
 drivers/pci/endpoint/functions/Makefile                   |   5 ++
 drivers/pci/endpoint/functions/pci-epf-test.c             | 510 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/endpoint/pci-ep-cfs.c                         | 509 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/endpoint/pci-epc-core.c                       | 579 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/pci/endpoint/pci-epc-mem.c                        | 143 +++++++++++++++++++++++++++++++++++
 drivers/pci/endpoint/pci-epf-core.c                       | 351 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/linux/mod_devicetable.h                           |  10 +++
 include/linux/pci-ep-cfs.h                                |  41 ++++++++++
 include/linux/pci-epc.h                                   | 144 +++++++++++++++++++++++++++++++++++
 include/linux/pci-epf.h                                   | 162 +++++++++++++++++++++++++++++++++++++++
 include/linux/pci_ids.h                                   |   2 +
 include/uapi/linux/Kbuild                                 |   1 +
 include/uapi/linux/pcitest.h                              |  19 +++++
 tools/pci/pcitest.c                                       | 186 +++++++++++++++++++++++++++++++++++++++++++++
 tools/pci/pcitest.sh                                      |  56 ++++++++++++++
 40 files changed, 4873 insertions(+), 40 deletions(-)
 create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt
 create mode 100644 Documentation/PCI/endpoint/pci-endpoint-cfs.txt
 create mode 100644 Documentation/PCI/endpoint/pci-endpoint.txt
 create mode 100644 Documentation/PCI/endpoint/pci-test-function.txt
 create mode 100644 Documentation/PCI/endpoint/pci-test-howto.txt
 create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt
 create mode 100644 drivers/misc/pci_endpoint_test.c
 create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
 create mode 100644 drivers/pci/endpoint/Kconfig
 create mode 100644 drivers/pci/endpoint/Makefile
 create mode 100644 drivers/pci/endpoint/functions/Kconfig
 create mode 100644 drivers/pci/endpoint/functions/Makefile
 create mode 100644 drivers/pci/endpoint/functions/pci-epf-test.c
 create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
 create mode 100644 drivers/pci/endpoint/pci-epc-core.c
 create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
 create mode 100644 drivers/pci/endpoint/pci-epf-core.c
 create mode 100644 include/linux/pci-ep-cfs.h
 create mode 100644 include/linux/pci-epc.h
 create mode 100644 include/linux/pci-epf.h
 create mode 100644 include/uapi/linux/pcitest.h
 create mode 100644 tools/pci/pcitest.c
 create mode 100644 tools/pci/pcitest.sh

Comments

Rob Herring March 20, 2017, 9:43 p.m.
On Mon, Mar 13, 2017 at 07:52:51PM +0530, Kishon Vijay Abraham I wrote:
> Update device tree binding documentation of TI's dra7xx PCI
> controller to include property for enabling unaligned mem access.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
> index 190828a5f32a..b69dd7dbd29e 100644
> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
> @@ -39,6 +39,11 @@ DEVICE MODE
>   - interrupts : one interrupt entries must be specified for main interrupt.
>   - num-ib-windows : number of inbound address translation windows
>   - num-ob-windows : number of outbound address translation windows
> + - ti,syscon-unaligned-access: phandle to the syscon dt node. The 1st argument
> +			       should contain the register offset within syscon
> +			       and the 2nd argument should contain the bit field
> +			       for setting the bit to enable unaligned
> +			       access.

This should be setup by the firmware/bootloader or some platform code. 
Why does the PCI host need to configure this?

Rob
Rob Herring March 20, 2017, 9:48 p.m.
On Mon, Mar 13, 2017 at 07:52:50PM +0530, Kishon Vijay Abraham I wrote:
> According to errata i870, access to the PCIe slave port
> that are not 32-bit aligned will result in incorrect mapping
> to TLP Address and Byte enable fields.
> 
> Accessing non 32-bit aligned data causes incorrect data in the target
> buffer if memcpy is used. Implement the workaround for this
> errata here.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>  drivers/pci/dwc/pci-dra7xx.c | 53 ++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 53 insertions(+)
> 
> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
> index 35c18534469c..147d37a7fe58 100644
> --- a/drivers/pci/dwc/pci-dra7xx.c
> +++ b/drivers/pci/dwc/pci-dra7xx.c
> @@ -26,6 +26,8 @@
>  #include <linux/pm_runtime.h>
>  #include <linux/resource.h>
>  #include <linux/types.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/regmap.h>
>  
>  #include "pcie-designware.h"
>  
> @@ -528,6 +530,51 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
>  	{},
>  };
>  
> +/*
> + * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
> + * @dra7xx: the dra7xx device where the workaround should be applied
> + *
> + * Access to the PCIe slave port that are not 32-bit aligned will result
> + * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
> + * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
> + * 0x3.
> + *
> + * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
> + */
> +static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
> +{
> +	int ret;
> +	struct device_node *np = dev->of_node;
> +	struct regmap *regmap;
> +	unsigned int reg;
> +	unsigned int field;
> +
> +	regmap = syscon_regmap_lookup_by_phandle(np,
> +						 "ti,syscon-unaligned-access");
> +	if (IS_ERR(regmap)) {
> +		dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
> +		return -EINVAL;
> +	}
> +
> +	if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 1,
> +				       &reg)) {
> +		dev_err(dev, "couldn't get legacy mode register offset\n");
> +		return -EINVAL;
> +	}
> +
> +	if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 2,
> +				       &field)) {
> +		dev_err(dev, "can't get bit field for setting legacy mode\n");
> +		return -EINVAL;
> +	}

If this remains, it's screaming for a helper function. 
of_parse_phandle_with_args already exists, but maybe a syscon specific 
function is in order.

> +
> +	ret = regmap_update_bits(regmap, reg, field, field);
> +	if (ret)
> +		dev_err(dev, "failed to enable unaligned access\n");
> +
> +	return ret;
> +}
> +
>  static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>  {
>  	u32 reg;
> @@ -637,6 +684,7 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>  	case DW_PCIE_RC_TYPE:
>  		dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
>  				   DEVICE_TYPE_RC);
> +

Unnecessary WS change.

>  		ret = dra7xx_add_pcie_port(dra7xx, pdev);
>  		if (ret < 0)
>  			goto err_gpio;
> @@ -644,6 +692,11 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
>  	case DW_PCIE_EP_TYPE:
>  		dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
>  				   DEVICE_TYPE_EP);
> +
> +		ret = dra7xx_pcie_ep_unaligned_memaccess(dev);
> +		if (ret)
> +			goto err_gpio;
> +
>  		ret = dra7xx_add_pcie_ep(dra7xx, pdev);
>  		if (ret < 0)
>  			goto err_gpio;
> -- 
> 2.11.0
> 
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Kishon Vijay Abraham I March 22, 2017, 2:37 p.m.
Hi Rob,

On Tuesday 21 March 2017 03:13 AM, Rob Herring wrote:
> On Mon, Mar 13, 2017 at 07:52:51PM +0530, Kishon Vijay Abraham I wrote:
>> Update device tree binding documentation of TI's dra7xx PCI
>> controller to include property for enabling unaligned mem access.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>  Documentation/devicetree/bindings/pci/ti-pci.txt | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> index 190828a5f32a..b69dd7dbd29e 100644
>> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
>> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
>> @@ -39,6 +39,11 @@ DEVICE MODE
>>   - interrupts : one interrupt entries must be specified for main interrupt.
>>   - num-ib-windows : number of inbound address translation windows
>>   - num-ob-windows : number of outbound address translation windows
>> + - ti,syscon-unaligned-access: phandle to the syscon dt node. The 1st argument
>> +			       should contain the register offset within syscon
>> +			       and the 2nd argument should contain the bit field
>> +			       for setting the bit to enable unaligned
>> +			       access.
> 
> This should be setup by the firmware/bootloader or some platform code. 
> Why does the PCI host need to configure this?

That would create a dependency between the bootloader and kernel which is
usually avoided in platforms like dra7xx.

Thanks
Kishon
Kishon Vijay Abraham I March 22, 2017, 2:39 p.m.
On Tuesday 21 March 2017 03:18 AM, Rob Herring wrote:
> On Mon, Mar 13, 2017 at 07:52:50PM +0530, Kishon Vijay Abraham I wrote:
>> According to errata i870, access to the PCIe slave port
>> that are not 32-bit aligned will result in incorrect mapping
>> to TLP Address and Byte enable fields.
>>
>> Accessing non 32-bit aligned data causes incorrect data in the target
>> buffer if memcpy is used. Implement the workaround for this
>> errata here.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>  drivers/pci/dwc/pci-dra7xx.c | 53 ++++++++++++++++++++++++++++++++++++++++++++
>>  1 file changed, 53 insertions(+)
>>
>> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
>> index 35c18534469c..147d37a7fe58 100644
>> --- a/drivers/pci/dwc/pci-dra7xx.c
>> +++ b/drivers/pci/dwc/pci-dra7xx.c
>> @@ -26,6 +26,8 @@
>>  #include <linux/pm_runtime.h>
>>  #include <linux/resource.h>
>>  #include <linux/types.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/regmap.h>
>>  
>>  #include "pcie-designware.h"
>>  
>> @@ -528,6 +530,51 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
>>  	{},
>>  };
>>  
>> +/*
>> + * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
>> + * @dra7xx: the dra7xx device where the workaround should be applied
>> + *
>> + * Access to the PCIe slave port that are not 32-bit aligned will result
>> + * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
>> + * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
>> + * 0x3.
>> + *
>> + * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
>> + */
>> +static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
>> +{
>> +	int ret;
>> +	struct device_node *np = dev->of_node;
>> +	struct regmap *regmap;
>> +	unsigned int reg;
>> +	unsigned int field;
>> +
>> +	regmap = syscon_regmap_lookup_by_phandle(np,
>> +						 "ti,syscon-unaligned-access");
>> +	if (IS_ERR(regmap)) {
>> +		dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 1,
>> +				       &reg)) {
>> +		dev_err(dev, "couldn't get legacy mode register offset\n");
>> +		return -EINVAL;
>> +	}
>> +
>> +	if (of_property_read_u32_index(np, "ti,syscon-unaligned-access", 2,
>> +				       &field)) {
>> +		dev_err(dev, "can't get bit field for setting legacy mode\n");
>> +		return -EINVAL;
>> +	}
> 
> If this remains, it's screaming for a helper function. 
> of_parse_phandle_with_args already exists, but maybe a syscon specific 
> function is in order.

hmm, I guess for now I can use of_parse_phandle_with_args. The number of args
might vary for different platforms/scenarios?

Thanks
Kishon