| Message ID | 1291195758-12322-1-git-send-email-Mingkai.hu@freescale.com (mailing list archive) |
|---|---|
| State | Accepted, archived |
| Delegated to: | Kumar Gala |
| Headers | show |
On Wed, Dec 01, 2010 at 05:29:18PM +0800, Mingkai Hu wrote: > The user must read N bytes of SPIRF (1 <= N <= 4) that do not exceed the > amount of data in the receive FIFO, so read the SPIRF byte by byte when > the data in receive FIFO is less than 4 bytes. > > On Simics, when read N bytes that exceed the amout of data in receive > FIFO, we can't read the data out, that is we can't clear the rx FIFO, > then the CPU will loop on the espi rx interrupt. > > Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Applied for -next, thanks. g. > --- > drivers/spi/spi_fsl_espi.c | 19 ++++++++++++++++--- > 1 files changed, 16 insertions(+), 3 deletions(-) > > diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c > index e3b4f64..ae78926 100644 > --- a/drivers/spi/spi_fsl_espi.c > +++ b/drivers/spi/spi_fsl_espi.c > @@ -507,16 +507,29 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) > > /* We need handle RX first */ > if (events & SPIE_NE) { > - u32 rx_data; > + u32 rx_data, tmp; > + u8 rx_data_8; > > /* Spin until RX is done */ > while (SPIE_RXCNT(events) < min(4, mspi->len)) { > cpu_relax(); > events = mpc8xxx_spi_read_reg(®_base->event); > } > - mspi->len -= 4; > > - rx_data = mpc8xxx_spi_read_reg(®_base->receive); > + if (mspi->len >= 4) { > + rx_data = mpc8xxx_spi_read_reg(®_base->receive); > + } else { > + tmp = mspi->len; > + rx_data = 0; > + while (tmp--) { > + rx_data_8 = in_8((u8 *)®_base->receive); > + rx_data |= (rx_data_8 << (tmp * 8)); > + } > + > + rx_data <<= (4 - mspi->len) * 8; > + } > + > + mspi->len -= 4; > > if (mspi->rx) > mspi->get_rx(rx_data, mspi); > -- > 1.7.0.4 > >
diff --git a/drivers/spi/spi_fsl_espi.c b/drivers/spi/spi_fsl_espi.c index e3b4f64..ae78926 100644 --- a/drivers/spi/spi_fsl_espi.c +++ b/drivers/spi/spi_fsl_espi.c @@ -507,16 +507,29 @@ void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) /* We need handle RX first */ if (events & SPIE_NE) { - u32 rx_data; + u32 rx_data, tmp; + u8 rx_data_8; /* Spin until RX is done */ while (SPIE_RXCNT(events) < min(4, mspi->len)) { cpu_relax(); events = mpc8xxx_spi_read_reg(®_base->event); } - mspi->len -= 4; - rx_data = mpc8xxx_spi_read_reg(®_base->receive); + if (mspi->len >= 4) { + rx_data = mpc8xxx_spi_read_reg(®_base->receive); + } else { + tmp = mspi->len; + rx_data = 0; + while (tmp--) { + rx_data_8 = in_8((u8 *)®_base->receive); + rx_data |= (rx_data_8 << (tmp * 8)); + } + + rx_data <<= (4 - mspi->len) * 8; + } + + mspi->len -= 4; if (mspi->rx) mspi->get_rx(rx_data, mspi);
The user must read N bytes of SPIRF (1 <= N <= 4) that do not exceed the amount of data in the receive FIFO, so read the SPIRF byte by byte when the data in receive FIFO is less than 4 bytes. On Simics, when read N bytes that exceed the amout of data in receive FIFO, we can't read the data out, that is we can't clear the rx FIFO, then the CPU will loop on the espi rx interrupt. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> --- drivers/spi/spi_fsl_espi.c | 19 ++++++++++++++++--- 1 files changed, 16 insertions(+), 3 deletions(-)