From patchwork Tue Nov 30 14:35:49 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 73725 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 24420B70AA for ; Wed, 1 Dec 2010 17:50:04 +1100 (EST) Received: from localhost ([127.0.0.1]:57008 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PNgVt-0001Rk-2a for incoming@patchwork.ozlabs.org; Wed, 01 Dec 2010 01:50:01 -0500 Received: from [140.186.70.92] (port=43808 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PNeVM-0006ZU-F9 for qemu-devel@nongnu.org; Tue, 30 Nov 2010 23:41:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PNRJX-0001Ii-Oa for qemu-devel@nongnu.org; Tue, 30 Nov 2010 09:36:17 -0500 Received: from cantor.suse.de ([195.135.220.2]:55556 helo=mx1.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PNRJX-0000zI-F7 for qemu-devel@nongnu.org; Tue, 30 Nov 2010 09:36:15 -0500 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 83A1494109; Tue, 30 Nov 2010 15:36:02 +0100 (CET) From: Alexander Graf To: QEMU-devel Developers Date: Tue, 30 Nov 2010 15:35:49 +0100 Message-Id: <1291127761-16501-4-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1291127761-16501-1-git-send-email-agraf@suse.de> References: <1291127761-16501-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 Cc: Blue Swirl , Paul Brook Subject: [Qemu-devel] [PATCH 03/15] Make simple io mem handler endian aware X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org As an alternative to the 3 individual handlers, there is also a simplified io mem hook function. To be consistent, let's add an endianness parameter there too. Signed-off-by: Alexander Graf --- hw/apb_pci.c | 3 ++- hw/pci_host.c | 12 ++++++++---- hw/unin_pci.c | 6 ++++-- rwhandler.c | 4 ++-- rwhandler.h | 2 +- 5 files changed, 17 insertions(+), 10 deletions(-) diff --git a/hw/apb_pci.c b/hw/apb_pci.c index bf00c71..84e9af7 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -418,7 +418,8 @@ static int pci_pbm_init_device(SysBusDevice *dev) /* PCI configuration space */ s->pci_config_handler.read = apb_pci_config_read; s->pci_config_handler.write = apb_pci_config_write; - pci_config = cpu_register_io_memory_simple(&s->pci_config_handler); + pci_config = cpu_register_io_memory_simple(&s->pci_config_handler, + DEVICE_NATIVE_ENDIAN); assert(pci_config >= 0); /* at region 1 */ sysbus_init_mmio(dev, 0x1000000ULL, pci_config); diff --git a/hw/pci_host.c b/hw/pci_host.c index bc5b771..a6e39c9 100644 --- a/hw/pci_host.c +++ b/hw/pci_host.c @@ -187,9 +187,11 @@ int pci_host_conf_register_mmio(PCIHostState *s, int swap) { pci_host_init(s); if (swap) { - return cpu_register_io_memory_simple(&s->conf_handler); + return cpu_register_io_memory_simple(&s->conf_handler, + DEVICE_NATIVE_ENDIAN); } else { - return cpu_register_io_memory_simple(&s->conf_noswap_handler); + return cpu_register_io_memory_simple(&s->conf_noswap_handler, + DEVICE_NATIVE_ENDIAN); } } @@ -203,9 +205,11 @@ int pci_host_data_register_mmio(PCIHostState *s, int swap) { pci_host_init(s); if (swap) { - return cpu_register_io_memory_simple(&s->data_handler); + return cpu_register_io_memory_simple(&s->data_handler, + DEVICE_NATIVE_ENDIAN); } else { - return cpu_register_io_memory_simple(&s->data_noswap_handler); + return cpu_register_io_memory_simple(&s->data_noswap_handler, + DEVICE_NATIVE_ENDIAN); } } diff --git a/hw/unin_pci.c b/hw/unin_pci.c index 1310211..53791dd 100644 --- a/hw/unin_pci.c +++ b/hw/unin_pci.c @@ -154,7 +154,8 @@ static int pci_unin_main_init_device(SysBusDevice *dev) pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1); s->data_handler.read = unin_data_read; s->data_handler.write = unin_data_write; - pci_mem_data = cpu_register_io_memory_simple(&s->data_handler); + pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, pci_mem_config); sysbus_init_mmio(dev, 0x1000, pci_mem_data); @@ -175,7 +176,8 @@ static int pci_u3_agp_init_device(SysBusDevice *dev) pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1); s->data_handler.read = unin_data_read; s->data_handler.write = unin_data_write; - pci_mem_data = cpu_register_io_memory_simple(&s->data_handler); + pci_mem_data = cpu_register_io_memory_simple(&s->data_handler, + DEVICE_NATIVE_ENDIAN); sysbus_init_mmio(dev, 0x1000, pci_mem_config); sysbus_init_mmio(dev, 0x1000, pci_mem_data); diff --git a/rwhandler.c b/rwhandler.c index 88dfcc5..bb2238f 100644 --- a/rwhandler.c +++ b/rwhandler.c @@ -35,14 +35,14 @@ static CPUReadMemoryFunc * const cpu_io_memory_simple_read[] = { &cpu_io_memory_simple_readl, }; -int cpu_register_io_memory_simple(struct ReadWriteHandler *handler) +int cpu_register_io_memory_simple(struct ReadWriteHandler *handler, int endian) { if (!handler->read || !handler->write) { return -1; } return cpu_register_io_memory(cpu_io_memory_simple_read, cpu_io_memory_simple_write, - handler, DEVICE_NATIVE_ENDIAN); + handler, endian); } RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t); diff --git a/rwhandler.h b/rwhandler.h index bc11849..b2a5790 100644 --- a/rwhandler.h +++ b/rwhandler.h @@ -19,7 +19,7 @@ struct ReadWriteHandler { /* Helpers for when we want to use a single routine with length. */ /* CPU memory handler: both read and write must be present. */ -int cpu_register_io_memory_simple(ReadWriteHandler *); +int cpu_register_io_memory_simple(ReadWriteHandler *, int endian); /* io port handler: can supply only read or write handlers. */ int register_ioport_simple(ReadWriteHandler *, pio_addr_t start, int length, int size);