From patchwork Fri Mar 10 00:25:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gavin Shan X-Patchwork-Id: 737193 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vfSkQ2T5Zz9s7f for ; Fri, 10 Mar 2017 11:26:54 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vfSkQ1ff9zDqXn for ; Fri, 10 Mar 2017 11:26:54 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vfSkL4jY4zDq5W for ; Fri, 10 Mar 2017 11:26:50 +1100 (AEDT) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v2A0NU5C145442 for ; Thu, 9 Mar 2017 19:26:48 -0500 Received: from e23smtp07.au.ibm.com (e23smtp07.au.ibm.com [202.81.31.140]) by mx0a-001b2d01.pphosted.com with ESMTP id 2937kmmvxs-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Thu, 09 Mar 2017 19:26:48 -0500 Received: from localhost by e23smtp07.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 10 Mar 2017 10:26:45 +1000 Received: from d23av05.au.ibm.com (d23av05.au.ibm.com [9.190.234.119]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v2A0Qawp40173742 for ; Fri, 10 Mar 2017 11:26:44 +1100 Received: from d23av05.au.ibm.com (localhost [127.0.0.1]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v2A0QCL6031620 for ; Fri, 10 Mar 2017 11:26:12 +1100 Received: from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14]) by d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v2A0QCt9031190; Fri, 10 Mar 2017 11:26:12 +1100 Received: from bran.ozlabs.ibm.com (haven.au.ibm.com [9.192.254.114]) by ozlabs.au.ibm.com (Postfix) with ESMTP id 024C9A01A5; Fri, 10 Mar 2017 11:25:48 +1100 (AEDT) Received: from gwshan.ozlabs.ibm.com (shangw.ozlabs.ibm.com [10.61.2.199]) by bran.ozlabs.ibm.com (Postfix) with ESMTP id E0C88E3A19; Fri, 10 Mar 2017 11:25:47 +1100 (AEDT) Received: by gwshan.ozlabs.ibm.com (Postfix, from userid 1000) id C466AAC0967; Fri, 10 Mar 2017 11:25:47 +1100 (AEDT) From: Gavin Shan To: skiboot@lists.ozlabs.org Date: Fri, 10 Mar 2017 11:25:45 +1100 X-Mailer: git-send-email 2.7.4 X-TM-AS-MML: disable x-cbid: 17031000-0044-0000-0000-000002350406 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17031000-0045-0000-0000-000006B1119C Message-Id: <1489105546-28092-1-git-send-email-gwshan@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-03-09_20:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1702020001 definitions=main-1703100002 Subject: [Skiboot] [PATCH 1/2] core/pci: Ignore PCI slot capability on root port X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" We are creating PCI slot on root port, where the PCI slot isn't supported from hardware. For this case, we shouldn't read the PCI slot capability from hardware. When bogus data returned from the hardware, we will attempt to the PCI slot's power state or enable surprise hotplug functionality. All of them can't be accomplished without hardware support. This leaves the PCI slot's capability list 0 if PCICAP_EXP_CAP_SLOT isn't set in hardware (pcie_cap + 0x2). Otherwise, the PCI slot's capability list is retrieved from hardware (pcie_cap + 0x14). Signed-off-by: Gavin Shan --- core/pcie-slot.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/core/pcie-slot.c b/core/pcie-slot.c index 64f0da6..aca59dd 100644 --- a/core/pcie-slot.c +++ b/core/pcie-slot.c @@ -461,8 +461,13 @@ struct pci_slot *pcie_slot_create(struct phb *phb, struct pci_device *pd) &slot->pcie_cap); pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_LCAP, &slot->link_cap); - pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCAP, - &slot->slot_cap); + + /* Leave PCI slot capability blank if PCI slot isn't supported */ + if (slot->pcie_cap & PCICAP_EXP_CAP_SLOT) + pci_cfg_read32(phb, pd->bdfn, ecap + PCICAP_EXP_SLOTCAP, + &slot->slot_cap); + else + slot->slot_cap = 0; if (slot->slot_cap & PCICAP_EXP_SLOTCAP_HPLUG_CAP) slot->pluggable = 1;