diff mbox

[U-Boot,v2,18/20] arm: socfpga: Add config and defconfig for Arria 10

Message ID 1489019218-4071-19-git-send-email-ley.foon.tan@intel.com
State Superseded
Delegated to: Marek Vasut
Headers show

Commit Message

Ley Foon Tan March 9, 2017, 12:26 a.m. UTC 
Add config and defconfig for the Arria10 and update socfpga_common.h.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 configs/socfpga_arria10_defconfig       | 30 +++++++++++++++
 include/configs/socfpga_arria10_socdk.h | 67 +++++++++++++++++++++++++++++++++
 include/configs/socfpga_common.h        | 28 ++++++++++++--
 3 files changed, 121 insertions(+), 4 deletions(-)
 create mode 100644 configs/socfpga_arria10_defconfig
 create mode 100644 include/configs/socfpga_arria10_socdk.h

Comments

Marek Vasut March 10, 2017, 1:55 a.m. UTC | #1 
On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
> Add config and defconfig for the Arria10 and update socfpga_common.h.
> 
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  configs/socfpga_arria10_defconfig       | 30 +++++++++++++++
>  include/configs/socfpga_arria10_socdk.h | 67 +++++++++++++++++++++++++++++++++
>  include/configs/socfpga_common.h        | 28 ++++++++++++--
>  3 files changed, 121 insertions(+), 4 deletions(-)
>  create mode 100644 configs/socfpga_arria10_defconfig
>  create mode 100644 include/configs/socfpga_arria10_socdk.h
> 
> diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
> new file mode 100644
> index 0000000..9e6bc1e0
> --- /dev/null
> +++ b/configs/socfpga_arria10_defconfig
> @@ -0,0 +1,30 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_SOCFPGA=y
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> +CONFIG_IDENT_STRING="socfpga_arria10"
> +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> +CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
> +CONFIG_SPL=y
> +CONFIG_CMD_BOOTZ=y
> +# CONFIG_CMD_IMLS is not set
> +CONFIG_CMD_ASKENV=y
> +CONFIG_CMD_GREPENV=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_CACHE=y
> +CONFIG_CMD_EXT4=y
> +CONFIG_CMD_EXT4_WRITE=y
> +CONFIG_DOS_PARTITION=y
> +# CONFIG_SPL_DOS_PARTITION is not set
> +CONFIG_SPL_DM=y
> +CONFIG_SPL_DM_SEQ_ALIAS=y
> +CONFIG_DM_GPIO=y
> +CONFIG_DWAPB_GPIO=y
> +CONFIG_DM_MMC=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_USE_TINY_PRINTF=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
> diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
> new file mode 100644
> index 0000000..5b7d572
> --- /dev/null
> +++ b/include/configs/socfpga_arria10_socdk.h
> @@ -0,0 +1,67 @@
> +/*
> + *  Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
> + *
> + * SPDX-License-Identifier:	GPL-2.0
> + */
> +
> +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
> +#define __CONFIG_SOCFGPA_ARRIA10_H__
> +
> +#include <asm/arch/base_addr_a10.h>
> +/* U-Boot Commands */
> +#define CONFIG_FAT_WRITE
> +#define CONFIG_HW_WATCHDOG
> +
> +

Drop this extra newline

> +/* Booting Linux */
> +#define CONFIG_LOADADDR		0x01000000
> +#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
> +
> +/*
> + * U-Boot general configurations
> + */
> +/* Cache options */
> +#define CONFIG_SYS_DCACHE_OFF
> +
> +/* Memory configurations  */
> +#define PHYS_SDRAM_1_SIZE		0x80000000
> +
> +/* Ethernet on SoC (EMAC) */
> +#if defined(CONFIG_CMD_NET)
> +#define CONFIG_PHY_MICREL
> +#define CONFIG_PHY_MICREL_KSZ9031
> +#endif
> +
> +/*
> + * U-Boot environment configurations
> + */
> +#define CONFIG_ENV_IS_IN_MMC
> +
> +/*
> + * arguments passed to the bootz command. The value of
> + * CONFIG_BOOTARGS goes into the environment value "bootargs".
> + * Do note the value will overide also the chosen node in FDT blob.
> + */
> +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
> +
> +/*
> + * Serial / UART configurations
> + */
> +#define CONFIG_SYS_NS16550_MEM32
> +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
> +
> +/*
> + * L4 OSC1 Timer 0
> + */
> +/* reload value when timer count to zero */
> +#define TIMER_LOAD_VAL			0xFFFFFFFF
> +
> +/*
> + * Flash configurations
> + */
> +#define CONFIG_SYS_MAX_FLASH_BANKS     1
> +
> +/* The rest of the configuration is shared */
> +#include <configs/socfpga_common.h>
> +
> +#endif	/* __CONFIG_SOCFGPA_ARRIA10_H__ */
> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
> index bc92a2c..a228ea5 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -34,9 +34,13 @@
>  #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
>  #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
>  #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
> -
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
>  #define CONFIG_SYS_INIT_RAM_SIZE	0x10000
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
> +#define CONFIG_SYS_INIT_RAM_SIZE	0x40000 /* 256KB */
> +#endif
>  #define CONFIG_SYS_INIT_SP_OFFSET		\
>  	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
>  #define CONFIG_SYS_INIT_SP_ADDR			\
> @@ -67,8 +71,10 @@
>  #define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
>  #endif
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #define CONFIG_CMD_PXE
>  #define CONFIG_MENU
> +#endif
>  
>  /*
>   * Cache
> @@ -103,13 +109,14 @@
>  /*
>   * FPGA Driver
>   */
> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>  #ifdef CONFIG_CMD_FPGA
>  #define CONFIG_FPGA
>  #define CONFIG_FPGA_ALTERA
>  #define CONFIG_FPGA_SOCFPGA
>  #define CONFIG_FPGA_COUNT		1
>  #endif
> -
> +#endif
>  /*
>   * L4 OSC1 Timer 0
>   */
> @@ -209,11 +216,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>   */
>  #define CONFIG_SYS_NS16550_SERIAL
>  #define CONFIG_SYS_NS16550_REG_SIZE	-4
> -#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
>  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
>  #define CONFIG_SYS_NS16550_CLK		1000000
> -#else
> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
> +#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
>  #define CONFIG_SYS_NS16550_CLK		100000000
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
> +#define CONFIG_SYS_NS16550_CLK		50000000
>  #endif
>  #define CONFIG_CONS_INDEX		1
>  #define CONFIG_BAUDRATE			115200
> @@ -301,7 +311,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>   */
>  #define CONFIG_SPL_FRAMEWORK
>  #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #define CONFIG_SPL_MAX_SIZE		(64 * 1024)

This should also be INIT_RAM_SIZE IMO   ^^

> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
> +#define CONFIG_SPL_BOARD_INIT
> +#endif
>  
>  /* SPL SDMMC boot support */
>  #ifdef CONFIG_SPL_MMC_SUPPORT
> @@ -349,10 +364,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  #define BOOT_TARGET_DEVICES_MMC(func)
>  #endif
>  
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>  #define BOOT_TARGET_DEVICES(func) \
>  	BOOT_TARGET_DEVICES_MMC(func) \
>  	BOOT_TARGET_DEVICES_PXE(func) \
>  	func(DHCP, dhcp, na)
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> +#define BOOT_TARGET_DEVICES(func) \
> +	BOOT_TARGET_DEVICES_MMC(func)
> +#endif
>  
>  #include <config_distro_bootcmd.h>
>  
>
Ley Foon Tan March 22, 2017, 8:39 a.m. UTC | #2 
On Fri, Mar 10, 2017 at 9:55 AM, Marek Vasut <marex@denx.de> wrote:
> On 03/09/2017 01:26 AM, Ley Foon Tan wrote:
>> Add config and defconfig for the Arria10 and update socfpga_common.h.
>>
>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>>  configs/socfpga_arria10_defconfig       | 30 +++++++++++++++
>>  include/configs/socfpga_arria10_socdk.h | 67 +++++++++++++++++++++++++++++++++
>>  include/configs/socfpga_common.h        | 28 ++++++++++++--
>>  3 files changed, 121 insertions(+), 4 deletions(-)
>>  create mode 100644 configs/socfpga_arria10_defconfig
>>  create mode 100644 include/configs/socfpga_arria10_socdk.h
>>
>> diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
>> new file mode 100644
>> index 0000000..9e6bc1e0
>> --- /dev/null
>> +++ b/configs/socfpga_arria10_defconfig
>> @@ -0,0 +1,30 @@
>> +CONFIG_ARM=y
>> +CONFIG_ARCH_SOCFPGA=y
>> +CONFIG_SYS_MALLOC_F_LEN=0x2000
>> +CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
>> +CONFIG_IDENT_STRING="socfpga_arria10"
>> +CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
>> +CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
>> +CONFIG_SPL=y
>> +CONFIG_CMD_BOOTZ=y
>> +# CONFIG_CMD_IMLS is not set
>> +CONFIG_CMD_ASKENV=y
>> +CONFIG_CMD_GREPENV=y
>> +# CONFIG_CMD_FLASH is not set
>> +CONFIG_CMD_MMC=y
>> +CONFIG_CMD_GPIO=y
>> +CONFIG_CMD_PING=y
>> +CONFIG_CMD_CACHE=y
>> +CONFIG_CMD_EXT4=y
>> +CONFIG_CMD_EXT4_WRITE=y
>> +CONFIG_DOS_PARTITION=y
>> +# CONFIG_SPL_DOS_PARTITION is not set
>> +CONFIG_SPL_DM=y
>> +CONFIG_SPL_DM_SEQ_ALIAS=y
>> +CONFIG_DM_GPIO=y
>> +CONFIG_DWAPB_GPIO=y
>> +CONFIG_DM_MMC=y
>> +CONFIG_SYS_NS16550=y
>> +CONFIG_USE_TINY_PRINTF=y
>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
>> +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
>> diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
>> new file mode 100644
>> index 0000000..5b7d572
>> --- /dev/null
>> +++ b/include/configs/socfpga_arria10_socdk.h
>> @@ -0,0 +1,67 @@
>> +/*
>> + *  Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
>> + *
>> + * SPDX-License-Identifier:  GPL-2.0
>> + */
>> +
>> +#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
>> +#define __CONFIG_SOCFGPA_ARRIA10_H__
>> +
>> +#include <asm/arch/base_addr_a10.h>
>> +/* U-Boot Commands */
>> +#define CONFIG_FAT_WRITE
>> +#define CONFIG_HW_WATCHDOG
>> +
>> +
>
> Drop this extra newline
Okay.
>
>> +/* Booting Linux */
>> +#define CONFIG_LOADADDR              0x01000000
>> +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
>> +
>> +/*
>> + * U-Boot general configurations
>> + */
>> +/* Cache options */
>> +#define CONFIG_SYS_DCACHE_OFF
>> +
>> +/* Memory configurations  */
>> +#define PHYS_SDRAM_1_SIZE            0x80000000
>> +
>> +/* Ethernet on SoC (EMAC) */
>> +#if defined(CONFIG_CMD_NET)
>> +#define CONFIG_PHY_MICREL
>> +#define CONFIG_PHY_MICREL_KSZ9031
>> +#endif
>> +
>> +/*
>> + * U-Boot environment configurations
>> + */
>> +#define CONFIG_ENV_IS_IN_MMC
>> +
>> +/*
>> + * arguments passed to the bootz command. The value of
>> + * CONFIG_BOOTARGS goes into the environment value "bootargs".
>> + * Do note the value will overide also the chosen node in FDT blob.
>> + */
>> +#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
>> +
>> +/*
>> + * Serial / UART configurations
>> + */
>> +#define CONFIG_SYS_NS16550_MEM32
>> +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
>> +
>> +/*
>> + * L4 OSC1 Timer 0
>> + */
>> +/* reload value when timer count to zero */
>> +#define TIMER_LOAD_VAL                       0xFFFFFFFF
>> +
>> +/*
>> + * Flash configurations
>> + */
>> +#define CONFIG_SYS_MAX_FLASH_BANKS     1
>> +
>> +/* The rest of the configuration is shared */
>> +#include <configs/socfpga_common.h>
>> +
>> +#endif       /* __CONFIG_SOCFGPA_ARRIA10_H__ */
>> diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
>> index bc92a2c..a228ea5 100644
>> --- a/include/configs/socfpga_common.h
>> +++ b/include/configs/socfpga_common.h
>> @@ -34,9 +34,13 @@
>>  #define CONFIG_SYS_MALLOC_LEN                (64 * 1024 * 1024)
>>  #define CONFIG_SYS_MEMTEST_START     PHYS_SDRAM_1
>>  #define CONFIG_SYS_MEMTEST_END               PHYS_SDRAM_1_SIZE
>> -
>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>  #define CONFIG_SYS_INIT_RAM_ADDR     0xFFFF0000
>>  #define CONFIG_SYS_INIT_RAM_SIZE     0x10000
>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> +#define CONFIG_SYS_INIT_RAM_ADDR     0xFFE00000
>> +#define CONFIG_SYS_INIT_RAM_SIZE     0x40000 /* 256KB */
>> +#endif
>>  #define CONFIG_SYS_INIT_SP_OFFSET            \
>>       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
>>  #define CONFIG_SYS_INIT_SP_ADDR                      \
>> @@ -67,8 +71,10 @@
>>  #define CONFIG_SYS_HOSTNAME  CONFIG_SYS_BOARD
>>  #endif
>>
>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>  #define CONFIG_CMD_PXE
>>  #define CONFIG_MENU
>> +#endif
>>
>>  /*
>>   * Cache
>> @@ -103,13 +109,14 @@
>>  /*
>>   * FPGA Driver
>>   */
>> +#ifdef CONFIG_TARGET_SOCFPGA_GEN5
>>  #ifdef CONFIG_CMD_FPGA
>>  #define CONFIG_FPGA
>>  #define CONFIG_FPGA_ALTERA
>>  #define CONFIG_FPGA_SOCFPGA
>>  #define CONFIG_FPGA_COUNT            1
>>  #endif
>> -
>> +#endif
>>  /*
>>   * L4 OSC1 Timer 0
>>   */
>> @@ -209,11 +216,14 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>   */
>>  #define CONFIG_SYS_NS16550_SERIAL
>>  #define CONFIG_SYS_NS16550_REG_SIZE  -4
>> -#define CONFIG_SYS_NS16550_COM1              SOCFPGA_UART0_ADDRESS
>>  #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
>>  #define CONFIG_SYS_NS16550_CLK               1000000
>> -#else
>> +#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
>> +#define CONFIG_SYS_NS16550_COM1              SOCFPGA_UART0_ADDRESS
>>  #define CONFIG_SYS_NS16550_CLK               100000000
>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> +#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
>> +#define CONFIG_SYS_NS16550_CLK               50000000
>>  #endif
>>  #define CONFIG_CONS_INDEX            1
>>  #define CONFIG_BAUDRATE                      115200
>> @@ -301,7 +311,12 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>   */
>>  #define CONFIG_SPL_FRAMEWORK
>>  #define CONFIG_SPL_TEXT_BASE         CONFIG_SYS_INIT_RAM_ADDR
>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>  #define CONFIG_SPL_MAX_SIZE          (64 * 1024)
>
> This should also be INIT_RAM_SIZE IMO   ^^
Yes, you are right. Will change this.
>
>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> +#define CONFIG_SPL_MAX_SIZE          CONFIG_SYS_INIT_RAM_SIZE
>> +#define CONFIG_SPL_BOARD_INIT
>> +#endif
>>
>>  /* SPL SDMMC boot support */
>>  #ifdef CONFIG_SPL_MMC_SUPPORT
>> @@ -349,10 +364,15 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>>  #define BOOT_TARGET_DEVICES_MMC(func)
>>  #endif
>>
>> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
>>  #define BOOT_TARGET_DEVICES(func) \
>>       BOOT_TARGET_DEVICES_MMC(func) \
>>       BOOT_TARGET_DEVICES_PXE(func) \
>>       func(DHCP, dhcp, na)
>> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
>> +#define BOOT_TARGET_DEVICES(func) \
>> +     BOOT_TARGET_DEVICES_MMC(func)
>> +#endif
>>
>>  #include <config_distro_bootcmd.h>
>>

Regards
Ley Foon
diff mbox

Patch

diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig
new file mode 100644
index 0000000..9e6bc1e0
--- /dev/null
+++ b/configs/socfpga_arria10_defconfig
@@ -0,0 +1,30 @@ 
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_arria10"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
+CONFIG_SPL=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_GREPENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_DOS_PARTITION=y
+# CONFIG_SPL_DOS_PARTITION is not set
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_DM_GPIO=y
+CONFIG_DWAPB_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_SYS_NS16550=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE=0xa2
diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h
new file mode 100644
index 0000000..5b7d572
--- /dev/null
+++ b/include/configs/socfpga_arria10_socdk.h
@@ -0,0 +1,67 @@ 
+/*
+ *  Copyright (C) 2015-2017 Altera Corporation <www.altera.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
+#define __CONFIG_SOCFGPA_ARRIA10_H__
+
+#include <asm/arch/base_addr_a10.h>
+/* U-Boot Commands */
+#define CONFIG_FAT_WRITE
+#define CONFIG_HW_WATCHDOG
+
+
+/* Booting Linux */
+#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+
+/*
+ * U-Boot general configurations
+ */
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE		0x80000000
+
+/* Ethernet on SoC (EMAC) */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_PHY_MICREL
+#define CONFIG_PHY_MICREL_KSZ9031
+#endif
+
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_IS_IN_MMC
+
+/*
+ * arguments passed to the bootz command. The value of
+ * CONFIG_BOOTARGS goes into the environment value "bootargs".
+ * Do note the value will overide also the chosen node in FDT blob.
+ */
+#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+
+/* The rest of the configuration is shared */
+#include <configs/socfpga_common.h>
+
+#endif	/* __CONFIG_SOCFGPA_ARRIA10_H__ */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index bc92a2c..a228ea5 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -34,9 +34,13 @@ 
 #define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
 #define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
 #define CONFIG_SYS_INIT_RAM_SIZE	0x10000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE	0x40000 /* 256KB */
+#endif
 #define CONFIG_SYS_INIT_SP_OFFSET		\
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR			\
@@ -67,8 +71,10 @@ 
 #define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_CMD_PXE
 #define CONFIG_MENU
+#endif
 
 /*
  * Cache
@@ -103,13 +109,14 @@ 
 /*
  * FPGA Driver
  */
+#ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
 #define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT		1
 #endif
-
+#endif
 /*
  * L4 OSC1 Timer 0
  */
@@ -209,11 +216,14 @@  unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	-4
-#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
 #define CONFIG_SYS_NS16550_CLK		1000000
-#else
+#elif defined(CONFIG_TARGET_SOCFPGA_GEN5)
+#define CONFIG_SYS_NS16550_COM1		SOCFPGA_UART0_ADDRESS
 #define CONFIG_SYS_NS16550_CLK		100000000
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_NS16550_CLK		50000000
 #endif
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_BAUDRATE			115200
@@ -301,7 +311,12 @@  unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SPL_MAX_SIZE		(64 * 1024)
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE
+#define CONFIG_SPL_BOARD_INIT
+#endif
 
 /* SPL SDMMC boot support */
 #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -349,10 +364,15 @@  unsigned int cm_get_qspi_controller_clk_hz(void);
 #define BOOT_TARGET_DEVICES_MMC(func)
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define BOOT_TARGET_DEVICES(func) \
 	BOOT_TARGET_DEVICES_MMC(func) \
 	BOOT_TARGET_DEVICES_PXE(func) \
 	func(DHCP, dhcp, na)
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#define BOOT_TARGET_DEVICES(func) \
+	BOOT_TARGET_DEVICES_MMC(func)
+#endif
 
 #include <config_distro_bootcmd.h>