From patchwork Wed Mar 8 08:02:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Jedrysek X-Patchwork-Id: 736495 X-Patchwork-Delegate: cyrille.pitchen@atmel.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vdR016FlNz9s8N for ; Wed, 8 Mar 2017 19:05:05 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="EX4eG01j"; dkim-atps=neutral DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20170209; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9nCSd0XIVpmz9TfA7FXUGE085pV0PkDV9Pdd0YrkWvA=; b=EX4eG01jhP07aS PkWgJQ8WbbJuLpRf6z1WCpSukRc4P9zhDC4hd7H9KpaD0nGbk55MeBfZQ8Z88LOZ+nIRuTJoguLb2 i++1mOnbmXumVi3FC5SD+mh+atZPI9djtszhnfp9LUSTK6LElOfs4w6dPBadznV5j1jq+fy6kcJW/ p4byof12W2Bm1cpVxZJ2ZhGRC0q8w8+Sm60tzPP/NRY+LBaKrSVwwq2+4MCg9Qn9KDo5t+5FMYEOF JQ01u7/3oARqNKNsbHlnqL9q5Sdc9Zl3bAXpSu5b7pkizpRlRYkIz1D5ulTOwFqdn8fYQrgc429Md rARJOVx46Di2Dlicuhuw==; Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1clWai-00069y-JP; Wed, 08 Mar 2017 08:05:00 +0000 Received: from mx0a-0014ca01.pphosted.com ([208.84.65.235]) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1clWa2-00066N-Ax for linux-mtd@lists.infradead.org; Wed, 08 Mar 2017 08:04:21 +0000 Received: from pps.filterd (m0042385.ppops.net [127.0.0.1]) by mx0a-0014ca01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v2882XKL006921; Wed, 8 Mar 2017 00:03:26 -0800 Received: from mx-sanjose.cadence.com (mx-sanjose.Cadence.COM [158.140.2.60]) by mx0a-0014ca01.pphosted.com with ESMTP id 29205nmeq9-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 08 Mar 2017 00:03:26 -0800 Received: from maileu3.global.cadence.com (maileu3.Cadence.COM [10.160.88.99]) by mx-sanjose.cadence.com (8.14.4/8.14.4) with ESMTP id v2882Xf2016699 (version=TLSv1/SSLv3 cipher=AES256-SHA bits=256 verify=FAIL); Wed, 8 Mar 2017 00:02:35 -0800 (PST) X-CrossPremisesHeadersFilteredBySendConnector: maileu3.global.cadence.com Received: from maileu3.global.cadence.com (10.160.88.99) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25; Wed, 8 Mar 2017 09:03:21 +0100 Received: from lvloginb.cadence.com (10.165.177.11) by maileu3.global.cadence.com (10.160.88.99) with Microsoft SMTP Server (TLS) id 15.0.1044.25 via Frontend Transport; Wed, 8 Mar 2017 09:03:21 +0100 Received: from lvloginb.cadence.com (localhost [127.0.0.1]) by lvloginb.cadence.com (8.14.4/8.14.4) with ESMTP id v2883H83011711; Wed, 8 Mar 2017 08:03:17 GMT Received: (from jartur@localhost) by lvloginb.cadence.com (8.14.4/8.14.4/Submit) id v2883Hip011710; Wed, 8 Mar 2017 08:03:17 GMT From: Artur Jedrysek To: Subject: [v2, 2/4] mtd: spi-nor: Add Octal SPI support to Cadence QSPI driver. Date: Wed, 8 Mar 2017 08:02:58 +0000 Message-ID: <1488960178-11079-1-git-send-email-jartur@cadence.com> X-Mailer: git-send-email 2.2.2 In-Reply-To: <1488959932-6657-1-git-send-email-jartur@cadence.com> References: <1488959932-6657-1-git-send-email-jartur@cadence.com> MIME-Version: 1.0 X-OrganizationHeadersPreserved: maileu3.global.cadence.com X-Received: by mx-sanjose.cadence.com as v2882Xf2016699 at Wed Mar 8 00:02:35 2017 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170308_000419_027064_2649FB96 X-CRM114-Status: GOOD ( 16.04 ) X-Spam-Score: -2.6 (--) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-2.6 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.7 RCVD_IN_DNSWL_LOW RBL: Sender listed at http://www.dnswl.org/, low trust [208.84.65.235 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-mtd@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Boris Brezillon , Artur Jedrysek , Richard Weinberger , linux-kernel@vger.kernel.org, Marek Vasut , Cyrille Pitchen , Brian Norris , David Woodhouse Sender: "linux-mtd" Errors-To: linux-mtd-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org Recent versions of Cadence QSPI controller support Octal SPI transfers as well. This patch updates existing driver to support such feature. It is not possible to determine whether or not octal mode is supported just by looking at revision register alone. To solve that, an additional compatible in Device Tree is added to indicate such capability. Both (revision and compatible) are used to determine, which mode to pass to spi_nor_scan() call. Signed-off-by: Artur Jedrysek --- Changelog: v2: Use new compatible in DT, instead of boolean property, to indicate Octal SPI support. Extracted Kconfig update to seperate patch. --- drivers/mtd/spi-nor/cadence-quadspi.c | 69 +++++++++++++++++++++++++++++++---- 1 file changed, 61 insertions(+), 8 deletions(-) diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c index 9f8102d..a96471d 100644 --- a/drivers/mtd/spi-nor/cadence-quadspi.c +++ b/drivers/mtd/spi-nor/cadence-quadspi.c @@ -76,6 +76,7 @@ struct cqspi_st { u32 fifo_depth; u32 fifo_width; u32 trigger_address; + u32 max_mode; struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT]; }; @@ -87,6 +88,10 @@ struct cqspi_st { #define CQSPI_INST_TYPE_SINGLE 0 #define CQSPI_INST_TYPE_DUAL 1 #define CQSPI_INST_TYPE_QUAD 2 +#define CQSPI_INST_TYPE_OCTAL 3 + +#define CQSPI_MAX_MODE_QUAD 0 +#define CQSPI_MAX_MODE_OCTAL 1 #define CQSPI_DUMMY_CLKS_PER_BYTE 8 #define CQSPI_DUMMY_BYTES_MAX 4 @@ -204,6 +209,14 @@ struct cqspi_st { #define CQSPI_REG_CMDWRITEDATALOWER 0xA8 #define CQSPI_REG_CMDWRITEDATAUPPER 0xAC +#define CQSPI_REG_MODULEID 0xFC +#define CQSPI_REG_MODULEID_CONF_ID_MASK 0x3 +#define CQSPI_REG_MODULEID_CONF_ID_LSB 0 +#define CQSPI_REG_MODULEID_CONF_ID_OCTAL_PHY 0x0 +#define CQSPI_REG_MODULEID_CONF_ID_OCTAL 0x1 +#define CQSPI_REG_MODULEID_CONF_ID_QUAD_PHY 0x2 +#define CQSPI_REG_MODULEID_CONF_ID_QUAD 0x3 + /* Interrupt status bits */ #define CQSPI_REG_IRQ_MODE_ERR BIT(0) #define CQSPI_REG_IRQ_UNDERFLOW BIT(1) @@ -866,6 +879,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read) case SPI_NOR_QUAD: f_pdata->data_width = CQSPI_INST_TYPE_QUAD; break; + case SPI_NOR_OCTAL: + f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; + break; default: return -EINVAL; } @@ -977,6 +993,17 @@ static int cqspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) return ret; } +static const u32 cqspi_max_mode_quad = CQSPI_MAX_MODE_QUAD; +static const u32 cqspi_max_mode_octal = CQSPI_MAX_MODE_OCTAL; + +static struct of_device_id const cqspi_dt_ids[] = { + { .compatible = "cdns,qspi-nor", .data = &cqspi_max_mode_quad }, + { .compatible = "cdns,ospi-nor", .data = &cqspi_max_mode_octal }, + { /* end of table */ } +}; + +MODULE_DEVICE_TABLE(of, cqspi_dt_ids); + static int cqspi_of_get_flash_pdata(struct platform_device *pdev, struct cqspi_flash_pdata *f_pdata, struct device_node *np) @@ -1018,6 +1045,13 @@ static int cqspi_of_get_pdata(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct cqspi_st *cqspi = platform_get_drvdata(pdev); + const struct of_device_id *match; + + cqspi->max_mode = CQSPI_MAX_MODE_QUAD; + + match = of_match_node(cqspi_dt_ids, np); + if (match && match->data) + cqspi->max_mode = *((u32 *)match->data); cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); @@ -1074,9 +1108,35 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) struct cqspi_flash_pdata *f_pdata; struct spi_nor *nor; struct mtd_info *mtd; + enum read_mode mode; + enum read_mode dt_mode = SPI_NOR_QUAD; unsigned int cs; + unsigned int rev_reg; int i, ret; + /* Determine, whether or not octal transfer MAY be supported */ + rev_reg = readl(cqspi->iobase + CQSPI_REG_MODULEID); + dev_info(dev, "CQSPI Module id %x\n", rev_reg); + + switch (rev_reg & CQSPI_REG_MODULEID_CONF_ID_MASK) { + case CQSPI_REG_MODULEID_CONF_ID_OCTAL_PHY: + case CQSPI_REG_MODULEID_CONF_ID_OCTAL: + mode = SPI_NOR_OCTAL; + break; + case CQSPI_REG_MODULEID_CONF_ID_QUAD: + case CQSPI_REG_MODULEID_CONF_ID_QUAD_PHY: + mode = SPI_NOR_QUAD; + break; + } + + if (cqspi->max_mode == CQSPI_MAX_MODE_OCTAL) + dt_mode = SPI_NOR_OCTAL; + + if (mode == SPI_NOR_QUAD && dt_mode == SPI_NOR_OCTAL) + dev_warn(dev, "Requested octal mode is not supported by the device."); + else if (mode == SPI_NOR_OCTAL && dt_mode == SPI_NOR_QUAD) + mode = SPI_NOR_QUAD; + /* Get flash device data */ for_each_available_child_of_node(dev->of_node, np) { ret = of_property_read_u32(np, "reg", &cs); @@ -1123,7 +1183,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np) goto err; } - ret = spi_nor_scan(nor, NULL, SPI_NOR_QUAD); + ret = spi_nor_scan(nor, NULL, mode); if (ret) goto err; @@ -1277,13 +1337,6 @@ static const struct dev_pm_ops cqspi__dev_pm_ops = { #define CQSPI_DEV_PM_OPS NULL #endif -static struct of_device_id const cqspi_dt_ids[] = { - {.compatible = "cdns,qspi-nor",}, - { /* end of table */ } -}; - -MODULE_DEVICE_TABLE(of, cqspi_dt_ids); - static struct platform_driver cqspi_platform_driver = { .probe = cqspi_probe, .remove = cqspi_remove,