Patchwork net/r8169: Correct the ram code for RTL8111D(L)

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Submitter fran├žois romieu
Date Nov. 29, 2010, 11:33 p.m.
Message ID <20101129233334.GA2888@electric-eye.fr.zoreil.com>
Download mbox | patch
Permalink /patch/73507/
State RFC
Delegated to: David Miller
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Comments

fran├žois romieu - Nov. 29, 2010, 11:33 p.m.
hayeswang <hayeswang@realtek.com> :
> Excuse me, I have some questions about the firmware patch.
> 
> 1. I should convert the data into the binary files (.bin). Is it right?

You may do it.

Fwiw I have cooked something for it in the attached patch #9 this WE. Feel
free to take bits from it. I will not do more changes while you work on it.

> 2. Where should I update the firmware files? Is the path the
> linux-2.6/firmware?

! This directory is only here to contain firmware images extracted from old
! device drivers which predate the common use of request_firmware().

It is fine for the existing code.

> However, according to linux-2.6/firmeware/README.AddingFirmware, I
> should update they to another repository:
> 	
> git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git

/me scratches head.

Assuming Realtek does not intend to stand this code / data as GPLable, yes.
It will help people staying clear from non-free code, it will help packaging
something useful and it will remove some cruft from the code.

So everybody will end happy. Especially after an aspirin.
stephen hemminger - Nov. 30, 2010, 12:13 a.m.
On Tue, 30 Nov 2010 00:33:34 +0100
Francois Romieu <romieu@fr.zoreil.com> wrote:

> hayeswang <hayeswang@realtek.com> :
> > Excuse me, I have some questions about the firmware patch.
> > 
> > 1. I should convert the data into the binary files (.bin). Is it right?
> 
> You may do it.
> 
> Fwiw I have cooked something for it in the attached patch #9 this WE. Feel
> free to take bits from it. I will not do more changes while you work on it.
> 
> > 2. Where should I update the firmware files? Is the path the
> > linux-2.6/firmware?
> 
> ! This directory is only here to contain firmware images extracted from old
> ! device drivers which predate the common use of request_firmware().
> 
> It is fine for the existing code.
> 
> > However, according to linux-2.6/firmeware/README.AddingFirmware, I
> > should update they to another repository:
> > 	
> > git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
> 
> /me scratches head.
> 
> Assuming Realtek does not intend to stand this code / data as GPLable, yes.
> It will help people staying clear from non-free code, it will help packaging
> something useful and it will remove some cruft from the code.
> 
> So everybody will end happy. Especially after an aspirin.

The plan is to do away with linux-2.6/firmware entirely.
Distributions are shipping the firmware from linux-firmware, not the
kernel files.
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hayeswang - Nov. 30, 2010, 6:37 a.m.
Hi Romieu,

Let me explain that not all of the phy settings are the ram code (or firmware).
Some of them are the initialization sequence. Only the "Low pass filter &
DLY_CAP fine tune from uC" is the firmware. And there is no firmware before
RTL8111D. That is, except 8111DP, the chips which have firmware are 8111d,
8111e,and 8105 now.

Now, I would modify my patch according to the example from Ben. And I would
update the firmware and licence to linux-firmware.

Thanks for everybody who help and answer to me.
 
Best Regards,
Hayes


> -----Original Message-----
> From: Stephen Hemminger [mailto:shemminger@vyatta.com] 
> Sent: Tuesday, November 30, 2010 8:14 AM
> To: Francois Romieu
> Cc: Hayeswang; 'Ben Hutchings'; netdev@vger.kernel.org; 
> linux-kernel@vger.kernel.org; 'David Miller'; 564628@bugs.debian.org
> Subject: Re: [PATCH] net/r8169: Correct the ram code for RTL8111D(L)
> 
> On Tue, 30 Nov 2010 00:33:34 +0100
> Francois Romieu <romieu@fr.zoreil.com> wrote:
> 
> > hayeswang <hayeswang@realtek.com> :
> > > Excuse me, I have some questions about the firmware patch.
> > > 
> > > 1. I should convert the data into the binary files 
> (.bin). Is it right?
> > 
> > You may do it.
> > 
> > Fwiw I have cooked something for it in the attached patch 
> #9 this WE. 
> > Feel free to take bits from it. I will not do more changes 
> while you work on it.
> > 
> > > 2. Where should I update the firmware files? Is the path the 
> > > linux-2.6/firmware?
> > 
> > ! This directory is only here to contain firmware images extracted 
> > from old ! device drivers which predate the common use of 
> request_firmware().
> > 
> > It is fine for the existing code.
> > 
> > > However, according to 
> linux-2.6/firmeware/README.AddingFirmware, I 
> > > should update they to another repository:
> > > 	
> > > 
> git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.g
> > > it
> > 
> > /me scratches head.
> > 
> > Assuming Realtek does not intend to stand this code / data 
> as GPLable, yes.
> > It will help people staying clear from non-free code, it will help 
> > packaging something useful and it will remove some cruft 
> from the code.
> > 
> > So everybody will end happy. Especially after an aspirin.
> 
> The plan is to do away with linux-2.6/firmware entirely.
> Distributions are shipping the firmware from linux-firmware, 
> not the kernel files.
> 
> 
> ------Please consider the environment before printing this e-mail. 
> 
> 

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Patch

diff --git a/drivers/net/r8169.c b/drivers/net/r8169.c
index 7d33ef4..114b9ce 100644
--- a/drivers/net/r8169.c
+++ b/drivers/net/r8169.c
@@ -1718,6 +1718,7 @@  static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
 {
 	static const struct phy_reg phy_reg_init_0[] = {
+		/* Channel Estimation */
 		{ 0x1f, 0x0001 },
 		{ 0x06, 0x4064 },
 		{ 0x07, 0x2863 },
@@ -1734,19 +1735,33 @@  static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
 		{ 0x12, 0xf49f },
 		{ 0x13, 0x070b },
 		{ 0x1a, 0x05ad },
-		{ 0x14, 0x94c0 }
-	};
-	static const struct phy_reg phy_reg_init_1[] = {
+		{ 0x14, 0x94c0 },
+
+		/*
+		 * Tx Error Issue
+		 * enhance line driver power
+		 */
 		{ 0x1f, 0x0002 },
 		{ 0x06, 0x5561 },
 		{ 0x1f, 0x0005 },
 		{ 0x05, 0x8332 },
-		{ 0x06, 0x5561 }
+		{ 0x06, 0x5561 },
+
+		/*
+		 * Can not link to 1Gbps with bad cable
+		 * Decrease SNR threshold form 21.07dB to 19.04dB
+		 */
+		{ 0x1f, 0x0001 },
+		{ 0x17, 0x0cc0 },
+
+		{ 0x1f, 0x0000 },
+		{ 0x0d, 0xf880 }
 	};
 	static const struct phy_reg phy_reg_init_2[] = {
+		/* Low pass filter & DLY_CAP fine tune from uC */
 		{ 0x1f, 0x0005 },
-		{ 0x05, 0xffc2 },
-		{ 0x1f, 0x0005 },
+		{ 0x05, 0xfff6 },
+		{ 0x06, 0x0080 },
 		{ 0x05, 0x8000 },
 		{ 0x06, 0xf8f9 },
 		{ 0x06, 0xfaef },
@@ -2084,29 +2099,51 @@  static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
 		{ 0x06, 0xff01 },
 		{ 0x06, 0x4edd },
 		{ 0x06, 0xff01 },
-		{ 0x05, 0x83d4 },
-		{ 0x06, 0x8000 },
+		{ 0x06, 0xf8fa },
+		{ 0x06, 0xfbef },
+		{ 0x06, 0x79bf },
+		{ 0x06, 0xf822 },
+		{ 0x06, 0xd819 },
+		{ 0x06, 0xd958 },
+		{ 0x06, 0x849f },
+		{ 0x06, 0x09bf },
+		{ 0x06, 0x82be },
+		{ 0x06, 0xd682 },
+		{ 0x06, 0xc602 },
+		{ 0x06, 0x014f },
+		{ 0x06, 0xef97 },
+		{ 0x06, 0xfffe },
+		{ 0x06, 0xfc05 },
+		{ 0x06, 0x17ff },
+		{ 0x06, 0xfe01 },
+		{ 0x06, 0x1700 },
+		{ 0x06, 0x0102 },
 		{ 0x05, 0x83d8 },
 		{ 0x06, 0x8051 },
-		{ 0x02, 0x6010 },
+		{ 0x05, 0x83d6 },
+		{ 0x06, 0x82a0 },
+		{ 0x05, 0x83d4 },
+		{ 0x06, 0x8000 },
+		{ 0x02, 0x2010 },
 		{ 0x03, 0xdc00 },
+		{ 0x1f, 0x0000 },
+		{ 0x0b, 0x0600 },
+		{ 0x1f, 0x0005 },
 		{ 0x05, 0xfff6 },
 		{ 0x06, 0x00fc },
-		{ 0x1f, 0x0000 },
-
-		{ 0x1f, 0x0000 },
-		{ 0x0d, 0xf880 },
 		{ 0x1f, 0x0000 }
 	};
 
 	rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
 
+	/*
+	 * Rx Error Issue
+	 * Fine Tune Switching regulator parameter
+	 */
 	mdio_write(ioaddr, 0x1f, 0x0002);
 	mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
 	mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
 
-	rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
-
 	if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
 		static const struct phy_reg phy_reg_init[] = {
 			{ 0x1f, 0x0002 },
@@ -2147,20 +2184,28 @@  static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
 		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 	}
 
+	/* RSET couple improve */
 	mdio_write(ioaddr, 0x1f, 0x0002);
 	mdio_patch(ioaddr, 0x0d, 0x0300);
 	mdio_patch(ioaddr, 0x0f, 0x0010);
 
+	/* Fine tune PLL performance */
 	mdio_write(ioaddr, 0x1f, 0x0002);
 	mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
 	mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
 
-	rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
+	mdio_write(ioaddr, 0x1f, 0x0005);
+	mdio_write(ioaddr, 0x05, 0x001b);
+	if (mdio_read(ioaddr, 0x06) == 0xbf00)
+		rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
+
+	mdio_write(ioaddr, 0x1f, 0x0000);
 }
 
 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
 {
 	static const struct phy_reg phy_reg_init_0[] = {
+		/* Channel Estimation */
 		{ 0x1f, 0x0001 },
 		{ 0x06, 0x4064 },
 		{ 0x07, 0x2863 },
@@ -2179,16 +2224,31 @@  static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
 		{ 0x1a, 0x05ad },
 		{ 0x14, 0x94c0 },
 
+		/*
+		 * Tx Error Issue
+		 * enhance line driver power
+		 */
 		{ 0x1f, 0x0002 },
 		{ 0x06, 0x5561 },
 		{ 0x1f, 0x0005 },
 		{ 0x05, 0x8332 },
-		{ 0x06, 0x5561 }
+		{ 0x06, 0x5561 },
+
+		/*
+		 * Can not link to 1Gbps with bad cable
+		 * Decrease SNR threshold form 21.07dB to 19.04dB
+		 */
+		{ 0x1f, 0x0001 },
+		{ 0x17, 0x0cc0 },
+
+		{ 0x1f, 0x0000 },
+		{ 0x0d, 0xf880 }
 	};
 	static const struct phy_reg phy_reg_init_1[] = {
+		/* Low pass filter & DLY_CAP fine tune from uC */
 		{ 0x1f, 0x0005 },
-		{ 0x05, 0xffc2 },
-		{ 0x1f, 0x0005 },
+		{ 0x05, 0xfff6 },
+		{ 0x06, 0x0080 },
 		{ 0x05, 0x8000 },
 		{ 0x06, 0xf8f9 },
 		{ 0x06, 0xfaee },
@@ -2485,16 +2545,37 @@  static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
 		{ 0x06, 0xdfff },
 		{ 0x06, 0x014e },
 		{ 0x06, 0xddff },
-		{ 0x06, 0x0100 },
+		{ 0x06, 0x01f8 },
+		{ 0x06, 0xfafb },
+		{ 0x06, 0xef79 },
+		{ 0x06, 0xbff8 },
+		{ 0x06, 0x22d8 },
+		{ 0x06, 0x19d9 },
+		{ 0x06, 0x5884 },
+		{ 0x06, 0x9f09 },
+		{ 0x06, 0xbf82 },
+		{ 0x06, 0x6dd6 },
+		{ 0x06, 0x8275 },
+		{ 0x06, 0x0201 },
+		{ 0x06, 0x4fef },
+		{ 0x06, 0x97ff },
+		{ 0x06, 0xfefc },
+		{ 0x06, 0x0517 },
+		{ 0x06, 0xfffe },
+		{ 0x06, 0x0117 },
+		{ 0x06, 0x0001 },
+		{ 0x06, 0x0200 },
 		{ 0x05, 0x83d8 },
 		{ 0x06, 0x8000 },
+		{ 0x05, 0x83d6 },
+		{ 0x06, 0x824f },
+		{ 0x02, 0x2010 },
 		{ 0x03, 0xdc00 },
+		{ 0x1f, 0x0000 },
+		{ 0x0b, 0x0600 },
+		{ 0x1f, 0x0005 },
 		{ 0x05, 0xfff6 },
 		{ 0x06, 0x00fc },
-		{ 0x1f, 0x0000 },
-
-		{ 0x1f, 0x0000 },
-		{ 0x0d, 0xf880 },
 		{ 0x1f, 0x0000 }
 	};
 
@@ -2540,17 +2621,21 @@  static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
 		rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
 	}
 
+	/* Fine tune PLL performance */
 	mdio_write(ioaddr, 0x1f, 0x0002);
 	mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
 	mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
 
-	mdio_write(ioaddr, 0x1f, 0x0001);
-	mdio_write(ioaddr, 0x17, 0x0cc0);
-
+	/* Switching regulator Slew rate */
 	mdio_write(ioaddr, 0x1f, 0x0002);
 	mdio_patch(ioaddr, 0x0f, 0x0017);
 
-	rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
+	mdio_write(ioaddr, 0x1f, 0x0005);
+	mdio_write(ioaddr, 0x05, 0x001b);
+	if (mdio_read(ioaddr, 0x06) == 0xb300)
+		rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
+
+	mdio_write(ioaddr, 0x1f, 0x0000);
 }
 
 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)