| Message ID | 20170301070447.20255-8-wens@csie.org |
|---|---|
| State | Superseded |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
On Wed, Mar 01, 2017 at 03:04:42PM +0800, Chen-Yu Tsai wrote: > The PIO on the R40 SoC is mostly compatible with the A20. > Only a few pin functions for mmc2 were added to the PC > pingroup, to support 8 bit eMMCs. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Maxime
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c index 8d2bb18504ae..3f40e8383001 100644 --- a/drivers/gpio/sunxi_gpio.c +++ b/drivers/gpio/sunxi_gpio.c @@ -352,6 +352,7 @@ static const struct udevice_id sunxi_gpio_ids[] = { ID("allwinner,sun8i-a33-pinctrl", a_all), ID("allwinner,sun8i-a83t-pinctrl", a_all), ID("allwinner,sun8i-h3-pinctrl", a_all), + ID("allwinner,sun8i-r40-pinctrl", a_all), ID("allwinner,sun9i-a80-pinctrl", a_all), ID("allwinner,sun6i-a31-r-pinctrl", l_2), ID("allwinner,sun8i-a23-r-pinctrl", l_1),
The PIO on the R40 SoC is mostly compatible with the A20. Only a few pin functions for mmc2 were added to the PC pingroup, to support 8 bit eMMCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/gpio/sunxi_gpio.c | 1 + 1 file changed, 1 insertion(+)