| Message ID | 1488335129-12363-8-git-send-email-andre.przywara@arm.com |
|---|---|
| State | Accepted |
| Commit | 0cef6cbe3a50cc48f6d0d574297ccb06b67e0f65 |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
On 28 February 2017 at 19:25, Andre Przywara <andre.przywara@arm.com> wrote: > Not every SoC needs to set up the GIC interrupt controller, so link > think code only when the respective config option is set. > This shaves off some bytes from the SPL code size. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > arch/arm/lib/Makefile | 2 ++ > 1 file changed, 2 insertions(+) Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 166fa9e..71de1ca 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -44,7 +44,9 @@ ifdef CONFIG_CPU_V7M obj-y += interrupts_m.o else ifdef CONFIG_ARM64 obj-y += ccn504.o +ifneq ($(CONFIG_GICV2)$(CONFIG_GICV3),) obj-y += gic_64.o +endif obj-y += interrupts_64.o else obj-y += interrupts.o
Not every SoC needs to set up the GIC interrupt controller, so link think code only when the respective config option is set. This shaves off some bytes from the SPL code size. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- arch/arm/lib/Makefile | 2 ++ 1 file changed, 2 insertions(+)