[V2,5/5] NX: Describe device-tree changes for P9 NX compression engines

Submitted by Haren Myneni on Feb. 27, 2017, 7:28 a.m.

Details

Message ID 1488180524.19744.3.camel@hbabu-laptop
State New
Headers show

Commit Message

Haren Myneni Feb. 27, 2017, 7:28 a.m.
Describe device-tree entries needed for 842 and gzip compression
engines on P9 NX.

Signed-off-by: Haren Myneni <haren@us.ibm.com>
---
 doc/device-tree/nx.rst |   34 ++++++++++++++++++++++++++++++----
 1 files changed, 30 insertions(+), 4 deletions(-)

Patch hide | download patch | download mbox

diff --git a/doc/device-tree/nx.rst b/doc/device-tree/nx.rst
index 4c54d4b..8057213 100644
--- a/doc/device-tree/nx.rst
+++ b/doc/device-tree/nx.rst
@@ -11,11 +11,11 @@  With unique xscom and nx addresses.  Their compatible node contains
 "ibm,power-nx".
 
 
-NX 842 Coprocessor
-------------------
+NX Compression Coprocessor
+--------------------------
 
-This is the memory compression coprocessor, which uses the IBM proprietary
-842 compression algorithm and format.  Each nx node contains an 842 engine.
+This is the memory compression coprocessor. which uses the IBM proprietary
+842 compression algorithm and format. Each NX node contains an 842 engine.
 ::
 
    ibm,842-coprocessor-type	: CT value common to all 842 coprocessors
@@ -29,6 +29,32 @@  all 842 coprocessors in the system, the CT value will (should) be the same,
 while each will have a different CI value.  The driver can use CI 0 to allow
 the hardware to automatically select which coprocessor instance to use.
 
+On P9 or later, this compression coprocessor also supports standard GZIP/ZLIB
+compression algorithm and format. Virtual Accelerator Swirchboard (VAS) is used
+to access this coprocessor. VAS writes each request to receive FIFOs (RXFIFO)
+which are either high or normal priority  and these FIFOs are bound to
+coprocessor types (842 and gzip).
+
+VAS distinguishes NX requests for the target engines based on logical
+partition ID (lpid), process ID (pid) and Thread ID (tid). So to create unique
+(lpid, pid, tid) combination in the system, chip ID, coprocessor type and
+priority are assigned to lpid, pid and tid respectively. Each NX node contains
+high and normal FIFOs for each  842 and GZIP engines.
+::
+  /ibm,nx-842-high		: High priority 842 RxFIFO
+  /ibm,nx-842-normal		: Normal priority 842 RxFIFO
+  /ibm,nx-gzip-high		: High priority gzip RxFIFO
+  /ibm,nx-gzip-normal		: Normal priority gzip RxFIFO
+
+Each RxFIFO node contains: ::
+	rx-fifo-address		: RxFIFO buffer address
+	lpid			: Chip ID
+	pid			: Coprocessor type (either 842 or gzip)
+	tid			: Priority (either high or normal)
+
+During initialization, the driver invokes VAS interface for each coprocessor 
+type (842 and gzip) to configure the RxFIFO with rx_fifo_address, lpid, pid 
+and tid for high and nornmal priority FIFOs.
 
 NX RNG Coprocessor
 ------------------