From patchwork Mon Feb 27 07:27:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haren Myneni X-Patchwork-Id: 732722 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vWtbN2Njjz9sCg for ; Mon, 27 Feb 2017 18:28:00 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vWtbN1SKszDqHC for ; Mon, 27 Feb 2017 18:28:00 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vWtbJ3MgfzDqC0 for ; Mon, 27 Feb 2017 18:27:56 +1100 (AEDT) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v1R7NmVC020888 for ; Mon, 27 Feb 2017 02:27:54 -0500 Received: from e37.co.us.ibm.com (e37.co.us.ibm.com [32.97.110.158]) by mx0a-001b2d01.pphosted.com with ESMTP id 28u7b50va6-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 27 Feb 2017 02:27:54 -0500 Received: from localhost by e37.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 27 Feb 2017 00:27:50 -0700 Received: from b03cxnp08028.gho.boulder.ibm.com (b03cxnp08028.gho.boulder.ibm.com [9.17.130.20]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id 2F5111FF002B; Mon, 27 Feb 2017 00:27:27 -0700 (MST) Received: from b03ledav004.gho.boulder.ibm.com (b03ledav004.gho.boulder.ibm.com [9.17.130.235]) by b03cxnp08028.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v1R7ReIc14680518; Mon, 27 Feb 2017 00:27:40 -0700 Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D2BAD78037; Mon, 27 Feb 2017 00:27:40 -0700 (MST) Received: from [9.70.82.143] (unknown [9.70.82.143]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP id 3C04778038; Mon, 27 Feb 2017 00:27:40 -0700 (MST) From: Haren Myneni To: stewart@linux.vnet.ibm.com Date: Sun, 26 Feb 2017 23:27:36 -0800 Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17022707-0024-0000-0000-000016018548 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006691; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000204; SDB=6.00827597; UDB=6.00405529; IPR=6.00605115; BA=6.00005174; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00014451; XFM=3.00000011; UTC=2017-02-27 07:27:52 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17022707-0025-0000-0000-00004913D97B Message-Id: <1488180456.19744.1.camel@hbabu-laptop> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-27_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702270075 Subject: [Skiboot] [PATCH v2 4/5] NX: Add P9 NX support for gzip compression engine X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xinhui@linux.vnet.ibm, hbabu@us.ibm.com, apopple@au1.ibm.com, skiboot@lists.ozlabs.org, michael.neuling@au1.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Power 9 introduces NX gzip compression engine. This patch adds gzip compression support in NX. Virtual Accelerator Switch (VAS) is used to access NX gzip engine and the channel configuration will be done with the recieve FIFO. So RxFIFO address, logical partition ID (lpid), process ID (pid) and thread ID (tid) are used to configure RxFIFO. P9 NX supports high and normal priority FIFOS. Skiboot configures User Mode Access Control (UMAC) noitify match register with these values and also enables other registers to enable / disable the engine. Creates the following device-tree entries to provide RxFIFO address, lpid, pid and tid values so that kernel can drive P9 NX gzip engine. The following nodes are located under an xscom node: /xscom@/nx@ /ibm,nx-gzip-high : High priority gzip RxFIFO /ibm,nx-gzip-normal : Normal priority gzip RxFIFO Each RxFIFO node contains: rx-fifo-address : RxFIFO address lpid : Chip ID pid : gzip coprocessor type tid : Priority (either high or normal) Signed-off-by: Haren Myneni --- hw/Makefile.inc | 2 +- hw/nx-compress.c | 1 + hw/nx-gzip.c | 126 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/nx.h | 1 + 4 files changed, 129 insertions(+), 1 deletions(-) create mode 100644 hw/nx-gzip.c diff --git a/hw/Makefile.inc b/hw/Makefile.inc index 97c909e..d4c4fcc 100644 --- a/hw/Makefile.inc +++ b/hw/Makefile.inc @@ -2,7 +2,7 @@ SUBDIRS += hw HW_OBJS = xscom.o chiptod.o gx.o cec.o lpc.o lpc-uart.o psi.o HW_OBJS += homer.o slw.o occ.o fsi-master.o centaur.o -HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o +HW_OBJS += nx.o nx-rng.o nx-crypto.o nx-compress.o nx-842.o nx-gzip.o HW_OBJS += p7ioc.o p7ioc-inits.o p7ioc-phb.o HW_OBJS += phb3.o sfc-ctrl.o fake-rtc.o bt.o p8-i2c.o prd.o HW_OBJS += dts.o lpc-rtc.o npu.o npu-hw-procedures.o xive.o phb4.o diff --git a/hw/nx-compress.c b/hw/nx-compress.c index 2ba056a..afce2bf 100644 --- a/hw/nx-compress.c +++ b/hw/nx-compress.c @@ -214,6 +214,7 @@ void nx_create_compress_node(struct dt_node *node) return; p9_nx_enable_842(node, gcid, pb_base); + p9_nx_enable_gzip(node, gcid, pb_base); } else nx_enable_842(node, gcid, pb_base); } diff --git a/hw/nx-gzip.c b/hw/nx-gzip.c new file mode 100644 index 0000000..e805cf6 --- /dev/null +++ b/hw/nx-gzip.c @@ -0,0 +1,126 @@ +/* Copyright 2016 IBM Corp. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + * implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include +#include +#include +#include +#include +#include + +#define EE (1) /* enable gzip engine */ + +static int nx_cfg_gzip_umac(struct dt_node *node, u32 gcid, u32 pb_base) +{ + int rc; + u64 umac_bar, umac_ctrl, umac_notify; + struct dt_node *nx_node; + + nx_node = dt_new(node, "ibm,nx-gzip-high"); + umac_bar = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_BAR; + umac_ctrl = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_CTRL; + umac_notify = pb_base + NX_P9_GZIP_HIGH_PRI_RX_FIFO_NOTIFY_MATCH; + + rc = nx_cfg_rx_fifo(nx_node, gcid, umac_bar, umac_notify, umac_ctrl, + NX_CT_GZIP, RX_FIFO_HIGH_PRIORITY); + if (rc) + return rc; + + nx_node = dt_new(node, "ibm,nx-gzip-normal"); + umac_bar = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_BAR; + umac_ctrl = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_CTRL; + umac_notify = pb_base + NX_P9_GZIP_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH; + + rc = nx_cfg_rx_fifo(nx_node, gcid, umac_bar, umac_notify, umac_ctrl, + NX_CT_GZIP, RX_FIFO_NORMAL_PRIORITY); + + return rc; +} + +static int nx_cfg_gzip_dma(u32 gcid, u64 xcfg) +{ + u64 cfg; + int rc; + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_DMA_CFG_GZIP_COMPRESS_PREFETCH, cfg, + DMA_COMPRESS_PREFETCH); + cfg = SETFIELD(NX_DMA_CFG_GZIP_DECOMPRESS_PREFETCH, cfg, + DMA_DECOMPRESS_PREFETCH); + + cfg = SETFIELD(NX_DMA_CFG_GZIP_COMPRESS_MAX_RR, cfg, + DMA_COMPRESS_MAX_RR); + cfg = SETFIELD(NX_DMA_CFG_GZIP_DECOMPRESS_MAX_RR, cfg, + DMA_DECOMPRESS_MAX_RR); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: DMA config failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: DMA 0x%016lx\n", gcid, + (unsigned long)cfg); + + return rc; +} + +static int nx_cfg_gzip_ee(u32 gcid, u64 xcfg) +{ + u64 cfg; + int rc; + + rc = xscom_read(gcid, xcfg, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_P9_EE_CFG_CH4, cfg, EE); + + rc = xscom_write(gcid, xcfg, cfg); + if (rc) + prerror("NX%d: ERROR: Engine Enable failure %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: Engine Enable 0x%016lx\n", + gcid, (unsigned long)cfg); + + return rc; +} + +void p9_nx_enable_gzip(struct dt_node *node, u32 gcid, u32 pb_base) +{ + u64 cfg_dma, cfg_ee; + int rc; + + prlog(PR_INFO, "NX%d: gzip at 0x%x\n", gcid, pb_base); + + cfg_dma = pb_base + NX_P9_DMA_CFG; + cfg_ee = pb_base + NX_P9_EE_CFG; + + rc = nx_cfg_gzip_dma(gcid, cfg_dma); + if (rc) + return; + + rc = nx_cfg_gzip_ee(gcid, cfg_ee); + if (rc) + return; + + rc = nx_cfg_gzip_umac(node, gcid, pb_base); + if (rc) + return; + + prlog(PR_INFO, "NX%d: gzip Coprocessor Enabled\n", gcid); +} diff --git a/include/nx.h b/include/nx.h index c2b599d..0d3c0fe 100644 --- a/include/nx.h +++ b/include/nx.h @@ -408,6 +408,7 @@ extern void nx_create_compress_node(struct dt_node *); extern void nx_enable_842(struct dt_node *, u32 gcid, u32 pb_base); extern void p9_nx_enable_842(struct dt_node *, u32 gcid, u32 pb_base); +extern void p9_nx_enable_gzip(struct dt_node *, u32 gcid, u32 pb_base); extern int nx_cfg_rx_fifo(struct dt_node *node, u32 gcid, u64 umac_bar, u64 umac_notify, u64 umac_ctrl, u32 ct_type,