From patchwork Mon Feb 27 07:25:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Haren Myneni X-Patchwork-Id: 732719 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vWtY16vk4z9sCg for ; Mon, 27 Feb 2017 18:25:57 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vWtY167pyzDqHs for ; Mon, 27 Feb 2017 18:25:57 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vWtXq58rCzDqC0 for ; Mon, 27 Feb 2017 18:25:47 +1100 (AEDT) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v1R7O1ZC171846 for ; Mon, 27 Feb 2017 02:25:45 -0500 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0b-001b2d01.pphosted.com with ESMTP id 28u8vt6xet-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 27 Feb 2017 02:25:44 -0500 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 27 Feb 2017 00:25:39 -0700 Received: from b01cxnp22036.gho.pok.ibm.com (b01cxnp22036.gho.pok.ibm.com [9.57.198.26]) by d03dlp01.boulder.ibm.com (Postfix) with ESMTP id BC8BF1FF001F; Mon, 27 Feb 2017 00:25:15 -0700 (MST) Received: from b01ledav005.gho.pok.ibm.com (b01ledav005.gho.pok.ibm.com [9.57.199.110]) by b01cxnp22036.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v1R7PSUs54067306; Mon, 27 Feb 2017 07:25:28 GMT Received: from b01ledav005.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id ACB80AE03C; Mon, 27 Feb 2017 02:25:24 -0500 (EST) Received: from [9.70.82.143] (unknown [9.70.82.143]) by b01ledav005.gho.pok.ibm.com (Postfix) with ESMTP id AE886AE043; Mon, 27 Feb 2017 02:25:23 -0500 (EST) From: Haren Myneni To: stewart@linux.vnet.ibm.com Date: Sun, 26 Feb 2017 23:25:23 -0800 Mime-Version: 1.0 X-Mailer: Evolution 2.28.3 X-TM-AS-GCONF: 00 x-cbid: 17022707-0004-0000-0000-000011B32807 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00006691; HX=3.00000240; KW=3.00000007; PH=3.00000004; SC=3.00000204; SDB=6.00827597; UDB=6.00405529; IPR=6.00605114; BA=6.00005174; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00014451; XFM=3.00000011; UTC=2017-02-27 07:25:40 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17022707-0005-0000-0000-00007D691CF6 Message-Id: <1488180323.19200.1.camel@hbabu-laptop> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-27_05:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=1 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702270075 Subject: [Skiboot] [PATCH V2 3/5] NX: Add P9 NX support for 842 compression engine X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xinhui@linux.vnet.ibm, hbabu@us.ibm.com, apopple@au1.ibm.com, skiboot@lists.ozlabs.org, michael.neuling@au1.ibm.com Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" This patch adds changes needed for 842 compression engine on power 9. Virtual Accelerator Switch (VAS) is used to access NX 842 engine on P9 and the channel setup will be done with receive FIFO. So RxFIFO address, logical partition ID (lpid), process ID (pid) and thread ID (tid) are used for this setup. p9 NX supports high and normal priority FIFOs. skiboot is not involved to process data with 842 engine, but configures User Mode Access Control (UMAC) noitify match register with these values and export them to kernel with device-tree entries. Also configure registers to setup and enable / disable the engine with the appropriate registers. Creates the following device-tree entries to provide RxFIFO address, lpid, pid and tid values so that kernel can drive P9 NX 842 engine. The following nodes are located under an xscom node: /xscom@/nx@ /ibm,nx-842-high : High priority 842 RxFIFO /ibm,nx-842-normal : Normal priority 842 RxFIFO Each RxFIFO node contains: rx-fifo-address : RxFIFO address lpid : Chip ID pid : 842 coprocessor type tid : Priority (either high or normal) Signed-off-by: Haren Myneni --- hw/nx-842.c | 63 +++++++++++++++++-- hw/nx-compress.c | 187 +++++++++++++++++++++++++++++++++++++++++++++++++++++- include/nx.h | 4 + 3 files changed, 248 insertions(+), 6 deletions(-) diff --git a/hw/nx-842.c b/hw/nx-842.c index 031de03..e1e8553 100644 --- a/hw/nx-842.c +++ b/hw/nx-842.c @@ -20,6 +20,7 @@ #include #include #include +#include /* Configuration settings */ #define CFG_842_FC_ENABLE (0x1f) /* enable all 842 functions */ @@ -85,6 +86,31 @@ static int nx_cfg_842(u32 gcid, u64 xcfg) return rc; } +static int nx_cfg_842_umac(struct dt_node *node, u32 gcid, u32 pb_base) +{ + int rc; + u64 umac_bar, umac_ctrl, umac_notify; + struct dt_node *nx_node; + + nx_node = dt_new(node, "ibm,nx-842-high"); + umac_bar = pb_base + NX_P9_842_HIGH_PRI_RX_FIFO_BAR; + umac_ctrl = pb_base + NX_P9_842_HIGH_PRI_RX_FIFO_CTRL; + umac_notify = pb_base + NX_P9_842_HIGH_PRI_RX_FIFO_NOTIFY_MATCH; + rc = nx_cfg_rx_fifo(nx_node, gcid, umac_bar, umac_notify, umac_ctrl, + NX_CT_842, RX_FIFO_HIGH_PRIORITY); + if (rc) + return rc; + + nx_node= dt_new(node, "ibm,nx-842-normal"); + umac_bar = pb_base + NX_P9_842_NORMAL_PRI_RX_FIFO_BAR; + umac_ctrl = pb_base + NX_P9_842_NORMAL_PRI_RX_FIFO_CTRL; + umac_notify = pb_base + NX_P9_842_NORMAL_PRI_RX_FIFO_NOTIFY_MATCH; + rc = nx_cfg_rx_fifo(nx_node, gcid, umac_bar, umac_notify, umac_ctrl, + NX_CT_842, RX_FIFO_NORMAL_PRIORITY); + + return rc; +} + static int nx_cfg_842_dma(u32 gcid, u64 xcfg) { u64 cfg; @@ -94,7 +120,7 @@ static int nx_cfg_842_dma(u32 gcid, u64 xcfg) if (rc) return rc; - if (proc_gen == proc_gen_p8) { + if (proc_gen >= proc_gen_p8) { cfg = SETFIELD(NX_DMA_CFG_842_COMPRESS_PREFETCH, cfg, DMA_COMPRESS_PREFETCH); cfg = SETFIELD(NX_DMA_CFG_842_DECOMPRESS_PREFETCH, cfg, @@ -107,14 +133,16 @@ static int nx_cfg_842_dma(u32 gcid, u64 xcfg) DMA_DECOMPRESS_MAX_RR); cfg = SETFIELD(NX_DMA_CFG_842_SPBC, cfg, DMA_SPBC); - cfg = SETFIELD(NX_DMA_CFG_842_CSB_WR, cfg, + if (proc_gen < proc_gen_p9) { + cfg = SETFIELD(NX_DMA_CFG_842_CSB_WR, cfg, DMA_CSB_WR); - cfg = SETFIELD(NX_DMA_CFG_842_COMPLETION_MODE, cfg, + cfg = SETFIELD(NX_DMA_CFG_842_COMPLETION_MODE, cfg, DMA_COMPLETION_MODE); - cfg = SETFIELD(NX_DMA_CFG_842_CPB_WR, cfg, + cfg = SETFIELD(NX_DMA_CFG_842_CPB_WR, cfg, DMA_CPB_WR); - cfg = SETFIELD(NX_DMA_CFG_842_OUTPUT_DATA_WR, cfg, + cfg = SETFIELD(NX_DMA_CFG_842_OUTPUT_DATA_WR, cfg, DMA_OUTPUT_DATA_WR); + } rc = xscom_write(gcid, xcfg, cfg); if (rc) @@ -183,3 +211,28 @@ void nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base) dt_add_property_cells(node, "ibm,842-coprocessor-type", NX_CT_842); dt_add_property_cells(node, "ibm,842-coprocessor-instance", gcid + 1); } + +void p9_nx_enable_842(struct dt_node *node, u32 gcid, u32 pb_base) +{ + u64 cfg_dma, cfg_ee; + int rc; + + cfg_dma = pb_base + NX_P9_DMA_CFG; + cfg_ee = pb_base + NX_P9_EE_CFG; + + rc = nx_cfg_842_dma(gcid, cfg_dma); + if (rc) + return; + + rc = nx_cfg_842_umac(node, gcid, pb_base); + if (rc) + return; + + rc = nx_cfg_842_ee(gcid, cfg_ee); + if (rc) + return; + + prlog(PR_INFO, "NX%d: 842 Coprocessor Enabled\n", gcid); + +} + diff --git a/hw/nx-compress.c b/hw/nx-compress.c index 2ea2734..2ba056a 100644 --- a/hw/nx-compress.c +++ b/hw/nx-compress.c @@ -20,15 +20,200 @@ #include #include #include +#include + +static int nx_cfg_umac_tx_wc(u32 gcid, u64 xcfg) +{ + int rc = 0; + u64 cfg; + + cfg = vas_get_wcbs_bar(gcid); + if (!cfg) { + prerror("NX%d: ERROR finding WC Backing store BAR\n", gcid); + return -ENOMEM; + } + + /* + * NOTE: Write the entire bar address to SCOM. VAS/NX will extract + * the relevant (NX_P9_UMAC_TX_WINDOW_CONTEXT_ADDR) bits. + * IOW, _don't_ just write the bit field like: + * + * cfg = SETFIELD(NX_P9_UMAC_TX_WINDOW_CONTEXT_ADDR, 0ULL, cfg); + */ + rc = xscom_write (gcid, xcfg, cfg); + + if (rc) + prerror("NX%d: ERROR: UMAC SEND WC BAR, %d\n", gcid, rc); + else + prlog(PR_DEBUG,"NX%d: UMAC SEND WC BAR, 0x%016lx, " + "xcfg 0x%llx\n", + gcid, (unsigned long)cfg, xcfg); + + return rc; +} + +static int nx_cfg_umac_vas_mmio(u32 gcid, u64 xcfg) +{ + int rc = 0; + u64 cfg; + + cfg = vas_get_hvwc_mmio_bar(gcid); + /* + * NOTE: Write the entire bar address to SCOM. VAS/NX will extract + * the relevant (NX_P9_UMAC_VAS_MMIO_ADDR) bits. IOW, _don't_ + * just write the bit field like: + * + * cfg = SETFIELD(NX_P9_UMAC_VAS_MMIO_ADDR, 0ULL, cfg); + */ + rc = xscom_write (gcid, xcfg, cfg); + + if (rc) + prerror("NX%d: ERROR: UMAC VAS MMIO BAR, %d\n", gcid, rc); + else + prlog(PR_DEBUG, "NX%d: UMAC VAS MMIO BAR, 0x%016lx, " + "xcfg 0x%llx\n", + gcid, (unsigned long)cfg, xcfg); + + return rc; +} + +static int nx_cfg_umac_status_ctrl(u32 gcid, u64 xcfg) +{ + u64 uctrl; + int rc; +#define CRB_ENABLE 1 + + rc = xscom_read(gcid, xcfg, &uctrl); + if (rc) + return rc; + + uctrl = SETFIELD(NX_P9_UMAC_STATUS_CTRL_CRB_ENABLE, uctrl, CRB_ENABLE); + rc = xscom_write(gcid, xcfg, uctrl); + if (rc) + prerror("NX%d: ERROR: Setting UMAC Status Control failure %d\n", + gcid, rc); + else + prlog(PR_DEBUG, "NX%d: Setting UMAC FIFO bar 0x%016lx\n", + gcid, (unsigned long)uctrl); + + return rc; +} + +int nx_cfg_rx_fifo(struct dt_node *node, u32 gcid, u64 umac_bar, + u64 umac_notify, u64 umac_ctrl, + u32 ct, u32 priority) +{ + u64 cfg; + int rc; + uint64_t fifo; +#define MATCH_ENABLE 1 +#define MAX_QUEUED 256 +#define HPRI_MAX_READ 256 + + fifo = (uint64_t) local_alloc(gcid, RX_FIFO_SIZE, RX_FIFO_SIZE); + assert(fifo); + + rc = xscom_read(gcid, umac_bar, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_P9_RX_FIFO_BAR_ADDR, cfg, fifo); + cfg = SETFIELD(NX_P9_RX_FIFO_BAR_SIZE, cfg, RX_FIFO_MAX_CRB_SIZE); + + rc = xscom_write(gcid, umac_bar, cfg); + if (rc) { + prerror("NX%d: ERROR: Setting UMAC FIFO bar failure %d\n", + gcid, rc); + return rc; + } else + prlog(PR_DEBUG, "NX%d: Setting UMAC FIFO bar 0x%016lx\n", + gcid, (unsigned long)cfg); + + rc = xscom_read(gcid, umac_notify, &cfg); + if (rc) + return rc; + + /* + * VAS issues asb_notify with the unique ID to identify the target + * co-processor/engine. Logical partition ID (lpid), process ID (pid), + * and thread ID (tid) combination is used to define the unique ID + * in the system. Export these values in device-tree such that the + * driver configure RxFIFO with VAS. Set these values in RxFIFO notify + * match register for each engine which compares the ID with each + * request. + * To define unique indentification, chip ID, co-processor type, and + * RxFIFO priority are used for lpid, pid, and tid respectively. + */ + cfg = SETFIELD(NX_P9_RX_FIFO_NOTIFY_MATCH_LPID, cfg, gcid + 1); + cfg = SETFIELD(NX_P9_RX_FIFO_NOTIFY_MATCH_PID, cfg, ct); + cfg = SETFIELD(NX_P9_RX_FIFO_NOTIFY_MATCH_TID, cfg, priority); + cfg = SETFIELD(NX_P9_RX_FIFO_NOTIFY_MATCH_MATCH_ENABLE, cfg, + MATCH_ENABLE); + + rc = xscom_write(gcid, umac_notify, cfg); + if (rc) { + prerror("NX%d: ERROR: Setting UMAC notify match failure %d\n", + gcid, rc); + return rc; + } else + prlog(PR_DEBUG, "NX%d: Setting UMAC notify match 0x%016lx\n", + gcid, (unsigned long)cfg); + + rc = xscom_read(gcid, umac_ctrl, &cfg); + if (rc) + return rc; + + cfg = SETFIELD(NX_P9_RX_FIFO_CTRL_QUEUED, cfg, MAX_QUEUED); + cfg = SETFIELD(NX_P9_RX_FIFO_CTRL_HPRI_MAX_READ, cfg, HPRI_MAX_READ); + + rc = xscom_write(gcid, umac_ctrl, cfg); + if (rc) { + prerror("NX%d: ERROR: Setting UMAC control failure %d\n", + gcid, rc); + return rc; + } else + prlog(PR_DEBUG, "NX%d: Setting UMAC control 0x%016lx\n", + gcid, (unsigned long)cfg); + + dt_add_property_u64(node, "rx-fifo-address", fifo); + dt_add_property_cells(node, "lpid", gcid + 1); + dt_add_property_cells(node, "pid", ct); + dt_add_property_cells(node, "tid", priority); + + return 0; +} void nx_create_compress_node(struct dt_node *node) { u32 gcid, pb_base; + int rc; gcid = dt_get_chip_id(node); pb_base = dt_get_address(node, 0, NULL); prlog(PR_INFO, "NX%d: 842 at 0x%x\n", gcid, pb_base); - nx_enable_842(node, gcid, pb_base); + if (dt_node_is_compatible(node, "ibm,power9-nx")) { + u64 cfg_mmio, cfg_txwc, cfg_uctrl; + + printf("Found ibm,power9-nx\n"); + cfg_mmio = pb_base + NX_P9_UMAC_VAS_MMIO_BAR; + cfg_txwc = pb_base + NX_P9_UMAC_TX_WINDOW_CONTEXT_BAR; + cfg_uctrl = pb_base + NX_P9_UMAC_STATUS_CTRL; + + rc = nx_cfg_umac_vas_mmio(gcid, cfg_mmio); + if (rc) + return; + + rc = nx_cfg_umac_tx_wc(gcid, cfg_txwc); + if (rc) + return; + + rc = nx_cfg_umac_status_ctrl(gcid, cfg_uctrl); + if (rc) + return; + + p9_nx_enable_842(node, gcid, pb_base); + } else + nx_enable_842(node, gcid, pb_base); } diff --git a/include/nx.h b/include/nx.h index 1a921ff..c2b599d 100644 --- a/include/nx.h +++ b/include/nx.h @@ -407,7 +407,11 @@ extern void nx_create_crypto_node(struct dt_node *); extern void nx_create_compress_node(struct dt_node *); extern void nx_enable_842(struct dt_node *, u32 gcid, u32 pb_base); +extern void p9_nx_enable_842(struct dt_node *, u32 gcid, u32 pb_base); +extern int nx_cfg_rx_fifo(struct dt_node *node, u32 gcid, u64 umac_bar, + u64 umac_notify, u64 umac_ctrl, u32 ct_type, + u32 priority); extern void nx_init(void); #endif /* __NX_H */