From patchwork Sun Feb 26 15:37:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 732547 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vWTWP1knGz9sDG for ; Mon, 27 Feb 2017 02:38:09 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vWTWP0rtfzDqH7 for ; Mon, 27 Feb 2017 02:38:09 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vWTWH2BZdzDqD0 for ; Mon, 27 Feb 2017 02:38:02 +1100 (AEDT) Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v1QFSSdZ115928 for ; Sun, 26 Feb 2017 10:38:00 -0500 Received: from e23smtp01.au.ibm.com (e23smtp01.au.ibm.com [202.81.31.143]) by mx0a-001b2d01.pphosted.com with ESMTP id 28u6y5at7s-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Sun, 26 Feb 2017 10:38:00 -0500 Received: from localhost by e23smtp01.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 27 Feb 2017 01:37:56 +1000 Received: from d23relay08.au.ibm.com (d23relay08.au.ibm.com [9.185.71.33]) by d23dlp02.au.ibm.com (Postfix) with ESMTP id E1E942BB0045 for ; Mon, 27 Feb 2017 02:37:55 +1100 (EST) Received: from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139]) by d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v1QFbl1E38076502 for ; Mon, 27 Feb 2017 02:37:55 +1100 Received: from d23av04.au.ibm.com (localhost [127.0.0.1]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id v1QFbNer026183 for ; Mon, 27 Feb 2017 02:37:23 +1100 Received: from drishya.in.ibm.com ([9.85.89.74]) by d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id v1QFbLJl026003; Mon, 27 Feb 2017 02:37:22 +1100 From: Vaidyanathan Srinivasan To: Michael Neuling , Stewart Smith Date: Sun, 26 Feb 2017 21:07:00 +0530 X-Mailer: git-send-email 2.9.3 X-TM-AS-MML: disable X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17022615-1617-0000-0000-000001AD009D X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17022615-1618-0000-0000-000047CE841A Message-Id: <20170226153700.31230-1-svaidy@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-26_11:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702260160 Subject: [Skiboot] [PATCH] hw/homer: Enable HOMER region reservation for POWER9 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" PBA BARs map various regions in HOMER memory used by STOP engines and OCC. Skip PBA BARs that have incomplete initialization and reserve the regions that are available in the system. Signed-off-by: Vaidyanathan Srinivasan --- hw/homer.c | 49 ++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 44 insertions(+), 5 deletions(-) diff --git a/hw/homer.c b/hw/homer.c index 84eb536..9ea1188 100644 --- a/hw/homer.c +++ b/hw/homer.c @@ -22,22 +22,39 @@ #include #include -#define PBA_BAR0 0x2013f00 -#define PBA_BARMASK0 0x2013f04 +#define P8_PBA_BAR0 0x2013f00 +#define P8_PBA_BARMASK0 0x2013f04 + +#define P9_PBA_BAR0 0x5012B00 +#define P9_PBA_BARMASK0 0x5012B04 + +#define PBA_MASK_ALL_BITS 0x000001FFFFF00000ULL /* Bits 23:43 */ static bool read_pba_bar(struct proc_chip *chip, unsigned int bar_no, uint64_t *base, uint64_t *size) { uint64_t bar, mask; + uint64_t pba_bar, pba_mask; int rc; - rc = xscom_read(chip->id, PBA_BAR0 + bar_no, &bar); + if (proc_gen == proc_gen_p8) { + pba_bar = P8_PBA_BAR0; + pba_mask = P8_PBA_BARMASK0; + } else if (proc_gen == proc_gen_p9) { + pba_bar = P9_PBA_BAR0; + pba_mask = P9_PBA_BARMASK0; + } else { + prerror("HOMER:read_pba_bar() Unknown processor, cannot find PBA BARs\n"); + return false; + } + + rc = xscom_read(chip->id, pba_bar + bar_no, &bar); if (rc) { prerror("SLW: Error %d reading PBA BAR%d on chip %d\n", rc, bar_no, chip->id); return false; } - rc = xscom_read(chip->id, PBA_BARMASK0 + bar_no, &mask); + rc = xscom_read(chip->id, pba_mask + bar_no, &mask); if (rc) { prerror("SLW: Error %d reading PBA BAR MASK%d on chip %d\n", rc, bar_no, chip->id); @@ -46,6 +63,16 @@ static bool read_pba_bar(struct proc_chip *chip, unsigned int bar_no, prlog(PR_DEBUG, " PBA BAR%d : 0x%016llx\n", bar_no, bar); prlog(PR_DEBUG, " PBA MASK%d: 0x%016llx\n", bar_no, mask); + if (mask == PBA_MASK_ALL_BITS) { + /* + * This could happen if all HOMER users are not enabled + * during early system bringup. Skip using the PBA BAR. + */ + mask = 0; + bar = 0; + prerror(" PBA MASK%d uninitalized skipping BAR\n", bar_no); + } + *base = bar & 0x0ffffffffffffffful; *size = (mask | 0xfffff) + 1; @@ -120,7 +147,9 @@ void homer_init(void) { struct proc_chip *chip; - if (proc_gen != proc_gen_p8 || chip_quirk(QUIRK_NO_PBA)) + if ((proc_gen != proc_gen_p8 && + proc_gen != proc_gen_p9) || + chip_quirk(QUIRK_NO_PBA)) return; /* @@ -140,6 +169,7 @@ void homer_init(void) */ chip = next_chip(NULL); + /* Both HOMER images and OCC areas are setup */ if (chip->homer_base && chip->occ_common_base) { /* Reserve OCC common area from BAR */ if (!mem_range_is_reserved(chip->occ_common_base, @@ -150,6 +180,15 @@ void homer_init(void) chip->occ_common_base, chip->occ_common_size); } + } else if (chip->homer_base) { + /* + * HOMER is setup but not OCC!! Do not allocate HOMER + * regions. This case is possible during early system bringup + * where OCC images are not yet operational. + */ + + prlog(PR_WARNING, + "HOMER base is setup, but not OCC common area!\n"); } else { /* Allocate memory for HOMER and OCC common area */ host_services_occ_base_setup();