| Message ID | 20170224034055.18807-5-afaerber@suse.de |
|---|---|
| State | New |
| Headers | show |
On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote: > Implement clocksource and clockevents for Actions Semi S500. > > Based on LeMaker linux-actions tree. > > Signed-off-by: Andreas Färber <afaerber@suse.de> As this is a new driver, please give some technical information about the driver itself and a pointer to documentation if it is publicly available. [ ... ] > +#define OWL_T0_CMP 0x0c > +#define OWL_T0_VAL 0x10 > +#define OWL_T1_CTL 0x14 > +#define OWL_T1_CMP 0x18 > +#define OWL_T1_VAL 0x1c > + > +#define OWL_Tx_CTL_INTEN (1 << 1) > +#define OWL_Tx_CTL_EN (1 << 2) s/(1 << 1)/BIT(1)/ s/(1 << 2)/BIT(2)/ > + > +static void __iomem *owl_timer_base; > + > +static u64 notrace owl_timer_sched_read(void) > +{ > + return (u64)readl(owl_timer_base + OWL_T0_VAL); > +} > + > +static int owl_timer_set_state_shutdown(struct clock_event_device *evt) > +{ > + writel(0, owl_timer_base + OWL_T1_CTL); > + > + return 0; > +} > + > +static int owl_timer_set_state_oneshot(struct clock_event_device *evt) > +{ > + writel(0, owl_timer_base + OWL_T1_CTL); > + writel(0, owl_timer_base + OWL_T1_VAL); > + writel(0, owl_timer_base + OWL_T1_CMP); > + > + return 0; > +} > + > +static int owl_timer_tick_resume(struct clock_event_device *evt) > +{ > + return 0; > +} > + > +static int owl_timer_set_next_event(unsigned long evt, > + struct clock_event_device *ev) > +{ > + writel(0, owl_timer_base + OWL_T1_CTL); > + > + writel(0, owl_timer_base + OWL_T1_VAL); > + writel(evt, owl_timer_base + OWL_T1_CMP); > + > + writel(OWL_Tx_CTL_EN | OWL_Tx_CTL_INTEN, owl_timer_base + OWL_T1_CTL); > + > + return 0; > +} > + > +static struct clock_event_device owl_clockevent = { > + .name = "owl_tick", > + .rating = 200, > + .features = CLOCK_EVT_FEAT_ONESHOT, Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ? > + .set_state_shutdown = owl_timer_set_state_shutdown, > + .set_state_oneshot = owl_timer_set_state_oneshot, > + .tick_resume = owl_timer_tick_resume, > + .set_next_event = owl_timer_set_next_event, > +}; > + > +static irqreturn_t owl_timer_interrupt(int irq, void *dev_id) > +{ > + struct clock_event_device *evt = (struct clock_event_device *)dev_id; > + > + evt->event_handler(evt); > + > + return IRQ_HANDLED; > +} > + > +static struct irqaction owl_timer_irq = { > + .name = "owl-timer", > + .flags = IRQF_TIMER, > + .handler = owl_timer_interrupt, > + .dev_id = &owl_clockevent, > +}; > + > +static int __init owl_timer_init(struct device_node *node) > +{ > + const unsigned long rate = 24000000; Use DT, either use clock-frequency or a clock ref. > + int irq1, ret; > + > + owl_timer_base = of_io_request_and_map(node, 0, "owl-timer"); > + if (IS_ERR(owl_timer_base)) { > + pr_err("Can't map timer registers"); > + return -ENXIO; Why not PTR_ERR(owl_timer_base) ? > + } > + > + irq1 = irq_of_parse_and_map(node, 1); > + if (irq1 <= 0) { > + pr_err("Can't parse timer1 IRQ"); > + return -EINVAL; > + } > + > + writel(0, owl_timer_base + OWL_T0_CTL); > + writel(0, owl_timer_base + OWL_T0_VAL); > + writel(0, owl_timer_base + OWL_T0_CMP); > + writel(OWL_Tx_CTL_EN, owl_timer_base + OWL_T0_CTL); Please factor out these calls into a function. > + > + sched_clock_register(owl_timer_sched_read, 32, rate); > + clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name, > + rate, 200, 32, clocksource_mmio_readl_up); > + > + writel(0, owl_timer_base + OWL_T1_CTL); > + writel(0, owl_timer_base + OWL_T1_VAL); > + writel(0, owl_timer_base + OWL_T1_CMP); > + > + ret = setup_irq(irq1, &owl_timer_irq); > + if (ret) { > + pr_warn("failed to setup irq %d\n", irq1); > + return ret; > + } s/setup_irq/request_irq/ > + > + owl_clockevent.cpumask = cpumask_of(0); > + owl_clockevent.irq = irq1; > + > + clockevents_config_and_register(&owl_clockevent, rate, > + 0xf, 0xffffffff); > + > + return 0; > +} > +CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init); Thanks ! -- Daniel
Am 24.02.2017 um 23:29 schrieb Daniel Lezcano: > On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote: >> Implement clocksource and clockevents for Actions Semi S500. >> >> Based on LeMaker linux-actions tree. >> >> Signed-off-by: Andreas Färber <afaerber@suse.de> > > As this is a new driver, please give some technical information about the > driver itself and a pointer to documentation if it is publicly available. What technical information would that be? Which of the timers we use as clock source vs. clock events? The only public documentation beyond the source tree mentioned is here: http://www.lemaker.org/product-guitar-download-29.html (section 3.4) >> +#define OWL_Tx_CTL_INTEN (1 << 1) >> +#define OWL_Tx_CTL_EN (1 << 2) > > s/(1 << 1)/BIT(1)/ > s/(1 << 2)/BIT(2)/ OK >> + >> +static void __iomem *owl_timer_base; >> + >> +static u64 notrace owl_timer_sched_read(void) >> +{ >> + return (u64)readl(owl_timer_base + OWL_T0_VAL); >> +} >> + >> +static int owl_timer_set_state_shutdown(struct clock_event_device *evt) >> +{ >> + writel(0, owl_timer_base + OWL_T1_CTL); >> + >> + return 0; >> +} >> + >> +static int owl_timer_set_state_oneshot(struct clock_event_device *evt) >> +{ >> + writel(0, owl_timer_base + OWL_T1_CTL); >> + writel(0, owl_timer_base + OWL_T1_VAL); >> + writel(0, owl_timer_base + OWL_T1_CMP); >> + >> + return 0; >> +} >> + >> +static int owl_timer_tick_resume(struct clock_event_device *evt) >> +{ >> + return 0; >> +} >> + >> +static int owl_timer_set_next_event(unsigned long evt, >> + struct clock_event_device *ev) >> +{ >> + writel(0, owl_timer_base + OWL_T1_CTL); >> + >> + writel(0, owl_timer_base + OWL_T1_VAL); >> + writel(evt, owl_timer_base + OWL_T1_CMP); >> + >> + writel(OWL_Tx_CTL_EN | OWL_Tx_CTL_INTEN, owl_timer_base + OWL_T1_CTL); >> + >> + return 0; >> +} >> + >> +static struct clock_event_device owl_clockevent = { >> + .name = "owl_tick", >> + .rating = 200, >> + .features = CLOCK_EVT_FEAT_ONESHOT, > > Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ? No, it was not present downstream. Got a good example? >> + .set_state_shutdown = owl_timer_set_state_shutdown, >> + .set_state_oneshot = owl_timer_set_state_oneshot, >> + .tick_resume = owl_timer_tick_resume, >> + .set_next_event = owl_timer_set_next_event, >> +}; >> + >> +static irqreturn_t owl_timer_interrupt(int irq, void *dev_id) >> +{ >> + struct clock_event_device *evt = (struct clock_event_device *)dev_id; >> + >> + evt->event_handler(evt); >> + >> + return IRQ_HANDLED; >> +} >> + >> +static struct irqaction owl_timer_irq = { >> + .name = "owl-timer", >> + .flags = IRQF_TIMER, >> + .handler = owl_timer_interrupt, >> + .dev_id = &owl_clockevent, >> +}; >> + >> +static int __init owl_timer_init(struct device_node *node) >> +{ >> + const unsigned long rate = 24000000; > > Use DT, either use clock-frequency or a clock ref. Are clk drivers really available at this point? clock-frequency sounds more promising. >> + int irq1, ret; >> + >> + owl_timer_base = of_io_request_and_map(node, 0, "owl-timer"); >> + if (IS_ERR(owl_timer_base)) { >> + pr_err("Can't map timer registers"); >> + return -ENXIO; > > Why not PTR_ERR(owl_timer_base) ? Only one in-tree driver (sun5i) matches such an expression. Will change. >> + } >> + >> + irq1 = irq_of_parse_and_map(node, 1); >> + if (irq1 <= 0) { >> + pr_err("Can't parse timer1 IRQ"); >> + return -EINVAL; >> + } >> + >> + writel(0, owl_timer_base + OWL_T0_CTL); >> + writel(0, owl_timer_base + OWL_T0_VAL); >> + writel(0, owl_timer_base + OWL_T0_CMP); >> + writel(OWL_Tx_CTL_EN, owl_timer_base + OWL_T0_CTL); > > Please factor out these calls into a function. Do you have something in particular in mind? Maybe ..._reset() for the first three? >> + >> + sched_clock_register(owl_timer_sched_read, 32, rate); >> + clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name, >> + rate, 200, 32, clocksource_mmio_readl_up); >> + >> + writel(0, owl_timer_base + OWL_T1_CTL); >> + writel(0, owl_timer_base + OWL_T1_VAL); >> + writel(0, owl_timer_base + OWL_T1_CMP); >> + >> + ret = setup_irq(irq1, &owl_timer_irq); >> + if (ret) { >> + pr_warn("failed to setup irq %d\n", irq1); >> + return ret; >> + } > > s/setup_irq/request_irq/ Care to explain? setup_irq has 32 hits vs. 28 for request_irq. >> + >> + owl_clockevent.cpumask = cpumask_of(0); >> + owl_clockevent.irq = irq1; >> + >> + clockevents_config_and_register(&owl_clockevent, rate, >> + 0xf, 0xffffffff); >> + >> + return 0; >> +} >> +CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init); Do you spot anything functionally wrong in this driver? Despite adding this new driver, I am only getting the following additional earlycon output: [ 0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns [ 0.007888] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns [ 0.017748] Console: colour dummy device 80x30 [ 0.022243] Calibrating delay loop... [ 0.030895] random: fast init done [ 0.231021] random: crng init done For S900 I'm using the generic timer instead. Thanks for your review, Andreas
On Sat, Feb 25, 2017 at 12:25:32AM +0100, Andreas Färber wrote: > Am 24.02.2017 um 23:29 schrieb Daniel Lezcano: > > On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote: > >> Implement clocksource and clockevents for Actions Semi S500. > >> > >> Based on LeMaker linux-actions tree. > >> > >> Signed-off-by: Andreas Färber <afaerber@suse.de> > > > > As this is a new driver, please give some technical information about the > > driver itself and a pointer to documentation if it is publicly available. > > What technical information would that be? Which of the timers we use as > clock source vs. clock events? Have a look at commit 07862c1 and e4a6b37 as reference. > The only public documentation beyond the source tree mentioned is here: > > http://www.lemaker.org/product-guitar-download-29.html (section 3.4) > > >> +#define OWL_Tx_CTL_INTEN (1 << 1) > >> +#define OWL_Tx_CTL_EN (1 << 2) > > > > s/(1 << 1)/BIT(1)/ > > s/(1 << 2)/BIT(2)/ > > OK > [ ... ] > >> +static struct clock_event_device owl_clockevent = { > >> + .name = "owl_tick", > >> + .rating = 200, > >> + .features = CLOCK_EVT_FEAT_ONESHOT, > > > > Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ? > > No, it was not present downstream. Got a good example? https://lwn.net/Articles/541000/ > >> + .set_state_shutdown = owl_timer_set_state_shutdown, > >> + .set_state_oneshot = owl_timer_set_state_oneshot, > >> + .tick_resume = owl_timer_tick_resume, > >> + .set_next_event = owl_timer_set_next_event, > >> +}; > >> + > >> +static irqreturn_t owl_timer_interrupt(int irq, void *dev_id) > >> +{ > >> + struct clock_event_device *evt = (struct clock_event_device *)dev_id; > >> + > >> + evt->event_handler(evt); > >> + > >> + return IRQ_HANDLED; > >> +} > >> + > >> +static struct irqaction owl_timer_irq = { > >> + .name = "owl-timer", > >> + .flags = IRQF_TIMER, > >> + .handler = owl_timer_interrupt, > >> + .dev_id = &owl_clockevent, > >> +}; > >> + > >> +static int __init owl_timer_init(struct device_node *node) > >> +{ > >> + const unsigned long rate = 24000000; > > > > Use DT, either use clock-frequency or a clock ref. > > Are clk drivers really available at this point? clock-frequency sounds > more promising. Yes they are. Have a look at the other drivers. > >> + int irq1, ret; > >> + > >> + owl_timer_base = of_io_request_and_map(node, 0, "owl-timer"); > >> + if (IS_ERR(owl_timer_base)) { > >> + pr_err("Can't map timer registers"); > >> + return -ENXIO; > > > > Why not PTR_ERR(owl_timer_base) ? > > Only one in-tree driver (sun5i) matches such an expression. Will change. [ ... ] > > Please factor out these calls into a function. > > Do you have something in particular in mind? Maybe ..._reset() for the > first three? Yes. > >> + > >> + sched_clock_register(owl_timer_sched_read, 32, rate); > >> + clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name, > >> + rate, 200, 32, clocksource_mmio_readl_up); > >> + > >> + writel(0, owl_timer_base + OWL_T1_CTL); > >> + writel(0, owl_timer_base + OWL_T1_VAL); > >> + writel(0, owl_timer_base + OWL_T1_CMP); > >> + > >> + ret = setup_irq(irq1, &owl_timer_irq); > >> + if (ret) { > >> + pr_warn("failed to setup irq %d\n", irq1); > >> + return ret; > >> + } > > > > s/setup_irq/request_irq/ > > Care to explain? setup_irq has 32 hits vs. 28 for request_irq. The function setup_irq takes an irqaction as parameter. That forces all the drivers to declare a structure, so for a multiple platforms support (aka single kernel image), there are multiple structures declaration for nothing. The function request_irq allocates the structure and then call setup_irq. So now, request_irq is used in place of setup_irq. > >> + > >> + owl_clockevent.cpumask = cpumask_of(0); > >> + owl_clockevent.irq = irq1; > >> + > >> + clockevents_config_and_register(&owl_clockevent, rate, > >> + 0xf, 0xffffffff); > >> + > >> + return 0; > >> +} > >> +CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init); > > Do you spot anything functionally wrong in this driver? Despite adding > this new driver, I am only getting the following additional earlycon output: > > [ 0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps > every 89478484971ns > [ 0.007888] clocksource: timer: mask: 0xffffffff max_cycles: > 0xffffffff, max_idle_ns: 79635851949 ns > [ 0.017748] Console: colour dummy device 80x30 > [ 0.022243] Calibrating delay loop... > [ 0.030895] random: fast init done > [ 0.231021] random: crng init done > > For S900 I'm using the generic timer instead. I don't get the issue, can you elaborate ? Thanks -- Daniel
Am 25.02.2017 um 22:59 schrieb Daniel Lezcano: > On Sat, Feb 25, 2017 at 12:25:32AM +0100, Andreas Färber wrote: >> Am 24.02.2017 um 23:29 schrieb Daniel Lezcano: >>> On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote: >>>> +static struct clock_event_device owl_clockevent = { >>>> + .name = "owl_tick", >>>> + .rating = 200, >>>> + .features = CLOCK_EVT_FEAT_ONESHOT, >>> >>> Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ? >> >> No, it was not present downstream. Got a good example? > > https://lwn.net/Articles/541000/ Looking at your current Nomadik code, it seems I can literally should just add this flag (done), without needing to implement any new hooks. On a related topic, how do we determine the cpumask? Downstream and some in-tree drivers use cpumask_of(0), others use cpu_possible_mask. >> Do you spot anything functionally wrong in this driver? Despite adding >> this new driver, I am only getting the following additional earlycon output: >> >> [ 0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps >> every 89478484971ns >> [ 0.007888] clocksource: timer: mask: 0xffffffff max_cycles: >> 0xffffffff, max_idle_ns: 79635851949 ns >> [ 0.017748] Console: colour dummy device 80x30 >> [ 0.022243] Calibrating delay loop... >> [ 0.030895] random: fast init done >> [ 0.231021] random: crng init done >> >> For S900 I'm using the generic timer instead. > > I don't get the issue, can you elaborate ? Found it myself: I forgot to clear the interrupt pending bit in the interrupt handler routine. + writel(OWL_Tx_CTL_PD, owl_timer_base + OWL_T1_CTL); Now it goes past this point, initializes the real serial driver and boots up to not finding the rootfs: [ 0.000032] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns [ 0.007898] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns [ 0.017886] Console: colour dummy device 80x30 [ 0.022386] Calibrating delay loop... 405.50 BogoMIPS (lpj=2027520) [ 0.083523] pid_max: default: 32768 minimum: 301 ... Regards, Andreas
On Sun, Feb 26, 2017 at 03:40:49PM +0100, Andreas Färber wrote: > Am 25.02.2017 um 22:59 schrieb Daniel Lezcano: > > On Sat, Feb 25, 2017 at 12:25:32AM +0100, Andreas Färber wrote: > >> Am 24.02.2017 um 23:29 schrieb Daniel Lezcano: > >>> On Fri, Feb 24, 2017 at 04:40:42AM +0100, Andreas Färber wrote: > >>>> +static struct clock_event_device owl_clockevent = { > >>>> + .name = "owl_tick", > >>>> + .rating = 200, > >>>> + .features = CLOCK_EVT_FEAT_ONESHOT, > >>> > >>> Did you consider adding CLOCK_EVT_FEAT_DYNIRQ ? > >> > >> No, it was not present downstream. Got a good example? > > > > https://lwn.net/Articles/541000/ > > Looking at your current Nomadik code, it seems I can literally should > just add this flag (done), without needing to implement any new hooks. > > On a related topic, how do we determine the cpumask? Downstream and some > in-tree drivers use cpumask_of(0), others use cpu_possible_mask. If you specify the CLOCK_EVT_FEAT_DYNIRQ, the cpumask is not important as it will be changed dynamically. Otherwise, cpumask_of(0) is often the default because it concentrates the wakeup on a single cpu, allowing the other cpus to go to deep idle state and if there are two clusters, it allows to have a cluster idle state. That results on a better energy saving. The usage of cpu_possible_mask will randomly wakeup any cpu. > >> Do you spot anything functionally wrong in this driver? Despite adding > >> this new driver, I am only getting the following additional earlycon output: > >> > >> [ 0.000029] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps > >> every 89478484971ns > >> [ 0.007888] clocksource: timer: mask: 0xffffffff max_cycles: > >> 0xffffffff, max_idle_ns: 79635851949 ns > >> [ 0.017748] Console: colour dummy device 80x30 > >> [ 0.022243] Calibrating delay loop... > >> [ 0.030895] random: fast init done > >> [ 0.231021] random: crng init done > >> > >> For S900 I'm using the generic timer instead. > > > > I don't get the issue, can you elaborate ? > > Found it myself: I forgot to clear the interrupt pending bit in the > interrupt handler routine. > > + writel(OWL_Tx_CTL_PD, owl_timer_base + OWL_T1_CTL); > > Now it goes past this point, initializes the real serial driver and > boots up to not finding the rootfs: > > [ 0.000032] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps > every 89478484971ns > [ 0.007898] clocksource: timer: mask: 0xffffffff max_cycles: > 0xffffffff, max_idle_ns: 79635851949 ns > [ 0.017886] Console: colour dummy device 80x30 > [ 0.022386] Calibrating delay loop... 405.50 BogoMIPS (lpj=2027520) May be you should also consider using register_current_timer_delay() instead of jiffies based delay loops. > [ 0.083523] pid_max: default: 32768 minimum: 301
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 3356ab8..2551365 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -107,6 +107,13 @@ config ORION_TIMER help Enables the support for the Orion timer driver +config OWL_TIMER + bool "Owl timer driver" if COMPILE_TEST + depends on GENERIC_CLOCKEVENTS + select CLKSRC_MMIO + help + Enables the support for the Actions Semi Owl timer driver. + config SUN4I_TIMER bool "Sun4i timer driver" if COMPILE_TEST depends on GENERIC_CLOCKEVENTS diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index d227d13..801b65a 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -53,6 +53,7 @@ obj-$(CONFIG_CLKSRC_PISTACHIO) += time-pistachio.o obj-$(CONFIG_CLKSRC_TI_32K) += timer-ti-32k.o obj-$(CONFIG_CLKSRC_NPS) += timer-nps.o obj-$(CONFIG_OXNAS_RPS_TIMER) += timer-oxnas-rps.o +obj-$(CONFIG_OWL_TIMER) += owl-timer.o obj-$(CONFIG_ARC_TIMERS) += arc_timer.o obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o diff --git a/drivers/clocksource/owl-timer.c b/drivers/clocksource/owl-timer.c new file mode 100644 index 0000000..e218ad7 --- /dev/null +++ b/drivers/clocksource/owl-timer.c @@ -0,0 +1,146 @@ +/* + * Actions Semi Owl timer + * + * Copyright 2012 Actions Semi Inc. + * Author: Actions Semi, Inc. + * + * Copyright (c) 2017 SUSE Linux GmbH + * Author: Andreas Färber + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/clockchips.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/irqreturn.h> +#include <linux/sched_clock.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/of_irq.h> + +#define OWL_T0_CTL 0x08 +#define OWL_T0_CMP 0x0c +#define OWL_T0_VAL 0x10 +#define OWL_T1_CTL 0x14 +#define OWL_T1_CMP 0x18 +#define OWL_T1_VAL 0x1c + +#define OWL_Tx_CTL_INTEN (1 << 1) +#define OWL_Tx_CTL_EN (1 << 2) + +static void __iomem *owl_timer_base; + +static u64 notrace owl_timer_sched_read(void) +{ + return (u64)readl(owl_timer_base + OWL_T0_VAL); +} + +static int owl_timer_set_state_shutdown(struct clock_event_device *evt) +{ + writel(0, owl_timer_base + OWL_T1_CTL); + + return 0; +} + +static int owl_timer_set_state_oneshot(struct clock_event_device *evt) +{ + writel(0, owl_timer_base + OWL_T1_CTL); + writel(0, owl_timer_base + OWL_T1_VAL); + writel(0, owl_timer_base + OWL_T1_CMP); + + return 0; +} + +static int owl_timer_tick_resume(struct clock_event_device *evt) +{ + return 0; +} + +static int owl_timer_set_next_event(unsigned long evt, + struct clock_event_device *ev) +{ + writel(0, owl_timer_base + OWL_T1_CTL); + + writel(0, owl_timer_base + OWL_T1_VAL); + writel(evt, owl_timer_base + OWL_T1_CMP); + + writel(OWL_Tx_CTL_EN | OWL_Tx_CTL_INTEN, owl_timer_base + OWL_T1_CTL); + + return 0; +} + +static struct clock_event_device owl_clockevent = { + .name = "owl_tick", + .rating = 200, + .features = CLOCK_EVT_FEAT_ONESHOT, + .set_state_shutdown = owl_timer_set_state_shutdown, + .set_state_oneshot = owl_timer_set_state_oneshot, + .tick_resume = owl_timer_tick_resume, + .set_next_event = owl_timer_set_next_event, +}; + +static irqreturn_t owl_timer_interrupt(int irq, void *dev_id) +{ + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static struct irqaction owl_timer_irq = { + .name = "owl-timer", + .flags = IRQF_TIMER, + .handler = owl_timer_interrupt, + .dev_id = &owl_clockevent, +}; + +static int __init owl_timer_init(struct device_node *node) +{ + const unsigned long rate = 24000000; + int irq1, ret; + + owl_timer_base = of_io_request_and_map(node, 0, "owl-timer"); + if (IS_ERR(owl_timer_base)) { + pr_err("Can't map timer registers"); + return -ENXIO; + } + + irq1 = irq_of_parse_and_map(node, 1); + if (irq1 <= 0) { + pr_err("Can't parse timer1 IRQ"); + return -EINVAL; + } + + writel(0, owl_timer_base + OWL_T0_CTL); + writel(0, owl_timer_base + OWL_T0_VAL); + writel(0, owl_timer_base + OWL_T0_CMP); + writel(OWL_Tx_CTL_EN, owl_timer_base + OWL_T0_CTL); + + sched_clock_register(owl_timer_sched_read, 32, rate); + clocksource_mmio_init(owl_timer_base + OWL_T0_VAL, node->name, + rate, 200, 32, clocksource_mmio_readl_up); + + writel(0, owl_timer_base + OWL_T1_CTL); + writel(0, owl_timer_base + OWL_T1_VAL); + writel(0, owl_timer_base + OWL_T1_CMP); + + ret = setup_irq(irq1, &owl_timer_irq); + if (ret) { + pr_warn("failed to setup irq %d\n", irq1); + return ret; + } + + owl_clockevent.cpumask = cpumask_of(0); + owl_clockevent.irq = irq1; + + clockevents_config_and_register(&owl_clockevent, rate, + 0xf, 0xffffffff); + + return 0; +} +CLOCKSOURCE_OF_DECLARE(owl, "actions,owl-timer", owl_timer_init);
Implement clocksource and clockevents for Actions Semi S500. Based on LeMaker linux-actions tree. Signed-off-by: Andreas Färber <afaerber@suse.de> --- v2: new drivers/clocksource/Kconfig | 7 ++ drivers/clocksource/Makefile | 1 + drivers/clocksource/owl-timer.c | 146 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 154 insertions(+) create mode 100644 drivers/clocksource/owl-timer.c