From patchwork Fri Nov 26 14:43:17 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Roese X-Patchwork-Id: 73182 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7E017B7080 for ; Sat, 27 Nov 2010 01:43:31 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D2EF128167; Fri, 26 Nov 2010 15:43:29 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id rrsUD-f3eov6; Fri, 26 Nov 2010 15:43:28 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2AB7428159; Fri, 26 Nov 2010 15:43:27 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0C0D828159 for ; Fri, 26 Nov 2010 15:43:26 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 67DPJFbLQfyH for ; Fri, 26 Nov 2010 15:43:24 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mo-p05-ob.rzone.de (mo-p05-ob.rzone.de [81.169.146.180]) by theia.denx.de (Postfix) with ESMTPS id 06B8528158 for ; Fri, 26 Nov 2010 15:43:22 +0100 (CET) X-RZG-AUTH: :IW0NeWC7b/q2i6W/qstXb1SBUuFnrGohavlCkce+Ub5QXMSOpHp3KJs5Kr5sMw== X-RZG-CLASS-ID: mo05 Received: from quad.fritz.box (p57BD4D96.dip.t-dialin.net [87.189.77.150]) by post.strato.de (klopstock mo59) (RZmta 24.6) with ESMTP id g01303mAQDGIZ3 for ; Fri, 26 Nov 2010 15:43:20 +0100 (MET) From: Stefan Roese To: u-boot@lists.denx.de Date: Fri, 26 Nov 2010 15:43:17 +0100 Message-Id: <1290782597-8883-1-git-send-email-sr@denx.de> X-Mailer: git-send-email 1.7.3.2 Subject: [U-Boot] [PATCH] ppc4xx: Clarify comment about boot chip-select in start.S X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Ths old comment was quite screwed up. Replace it with a new version that should be a bit more descriptive. Signed-off-by: Stefan Roese --- arch/powerpc/cpu/ppc4xx/start.S | 26 ++++++++++++++------------ 1 files changed, 14 insertions(+), 12 deletions(-) diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 65195f5..d77272c 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -48,21 +48,23 @@ *------------------------------------------------------------------------------- */ -/* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards - * +/* + * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards * - * The processor starts at 0xfffffffc and the code is executed - * from flash/rom. - * in memory, but as long we don't jump around before relocating. - * board_init lies at a quite high address and when the cpu has - * jumped there, everything is ok. - * This works because the cpu gives the FLASH (CS0) the whole - * address space at startup, and board_init lies as a echo of - * the flash somewhere up there in the memorymap. + * The following description only applies to the NOR flash style booting. + * NAND booting is different. For more details about NAND booting on 4xx + * take a look at doc/README.nand-boot-ppc440. * - * board_init will change CS0 to be positioned at the correct - * address and (s)dram will be positioned at address 0 + * The CPU starts at address 0xfffffffc (last word in the address space). + * The U-Boot image therefore has to be located in the "upper" area of the + * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for + * the boot chip-select (CS0) is quite big and covers this area. On the + * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will + * reconfigure this CS0 (and other chip-selects as well when configured + * this way) in the boot process to the "correct" values matching the + * board layout. */ + #include #include #include