[V2] slw: use only lite stop states for P9 DD1

Submitted by Shilpasri G Bhat on Feb. 23, 2017, 5:37 a.m.

Details

Message ID 1487828256-13999-1-git-send-email-shilpa.bhat@linux.vnet.ibm.com
State New
Headers show

Commit Message

Shilpasri G Bhat Feb. 23, 2017, 5:37 a.m.
POWER9 DD1 chip can work with lite stop states now. These
STOP states have ESL=EC=0 and provide fast entry/exit.

Signed-off-by: Shilpasri G Bhat <shilpa.bhat@linux.vnet.ibm.com>
Signed-off-by: Vaidyanathan Srinivasan <svaidy@linux.vnet.ibm.com>
---
Changes from V1:
- Removed only_lite variable.
- Moved the ESL check inside "if (has_stop_inst)"
 hw/slw.c | 5 +++++
 1 file changed, 5 insertions(+)

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diff --git a/hw/slw.c b/hw/slw.c
index 97d4758..45ea1d3 100644
--- a/hw/slw.c
+++ b/hw/slw.c
@@ -765,6 +765,11 @@  void add_cpu_idle_state_properties(void)
 		if (has_stop_inst) {
 			u32 level = 31 - (states[i].pm_ctrl_reg_val &
 					 OPAL_PM_PSSCR_RL_MASK);
+			u64 esl = states[i].pm_ctrl_reg_val &
+				  OPAL_PM_PSSCR_ESL;
+
+			if (chip->ec_level == 0x10 && esl)
+				continue;
 
 			if (!(stop_levels & (1ul << level)))
 				continue;