diff --git a/CREDITS b/CREDITS
index d681018..253abac 100644
--- a/CREDITS
+++ b/CREDITS
@@ -22,10 +22,6 @@ N: Guillaume Alexandre
 E: guillaume.alexandre@gespac.ch
 D: Add PCIPPC6 configuration
 
-N: Swen Anderson
-E: sand@peppercon.de
-D: ERIC Support
-
 N: Pantelis Antoniou
 E: panto@intracom.gr
 D: NETVIA & NETPHONE board support, ARTOS support.
diff --git a/MAINTAINERS b/MAINTAINERS
index 9258cb1..02a5ee0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -524,8 +524,6 @@ Unknown / orphaned boards:
 	RPXClassic	MPC8xx
 	RPXlite		MPC8xx
 
-	ERIC		PPC4xx
-
 	MOUSSE		MPC824x
 
 	RPXsuper	MPC8260
diff --git a/board/eric/Makefile b/board/eric/Makefile
deleted file mode 100644
index c690e33..0000000
--- a/board/eric/Makefile
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS	= $(BOARD).o flash.o
-SOBJS	= init.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/eric/eric.c b/board/eric/eric.c
deleted file mode 100644
index d431204..0000000
--- a/board/eric/eric.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <i2c.h>
-#include "eric.h"
-#include <asm/processor.h>
-
-#define PPC405GP_GPIO0_OR      0xef600700	/* GPIO Output */
-#define PPC405GP_GPIO0_TCR     0xef600704	/* GPIO Three-State Control */
-#define PPC405GP_GPIO0_ODR     0xef600718	/* GPIO Open Drain */
-#define PPC405GP_GPIO0_IR      0xef60071c	/* GPIO Input */
-
-void sdram_init(void);
-
-int board_early_init_f (void)
-{
-
-   /*-------------------------------------------------------------------------+
-   | Interrupt controller setup for the ERIC board.
-   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
-   |       IRQ 16    405GP internally generated; active low; level sensitive
-   |       IRQ 17-24 RESERVED
-   |       IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive
-   |       IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive
-   |       IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive
-   |                          indicates NO Power or HOST RESET active
-   |                          check GPIO7 (HOST RESET#) and GPIO8 (NO Power#)
-   |                          for real IRQ source
-   |       IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive
-   |       IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive
-   |       IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive
-   |       IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive
-   |        -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting
-   |           PPC405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in PPC405GP_GPIO0_OR,
-   |           else tristate)
-   | Note for ERIC board:
-   |       An interrupt taken for the HOST (IRQ 28) indicates that
-   |       the HOST wrote a "1" to one of the following locations
-   |       - VGA CRT_GPIO0 (if R1216 is loaded)
-   |       - VGA CRT_GPIO1 (if R1217 is loaded)
-   |
-   +-------------------------------------------------------------------------*/
-
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr (UIC0CR, 0x00000000);	/* set all SMI to be non-critical */
-	mtdcr (UIC0PR, 0xFFFFFF88);	/* set int polarities; IRQ3 to 1 */
-	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels, UART0 is EDGE */
-	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	mtdcr (CPC0_CR0, 0x00002000);	/* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
-
-	out32 (PPC405GP_GPIO0_OR, 0x60000000);	/*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
-	out32 (PPC405GP_GPIO0_TCR, 0x7E400000);
-
-	return 0;
-}
-
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * Check Board Identity:
- */
-
-int checkboard (void)
-{
-	char *s = getenv ("serial#");
-	char *e;
-
-	puts ("Board: ");
-
-	if (!s || strncmp (s, "ERIC", 9)) {
-		puts ("### No HW ID - assuming ERIC");
-	} else {
-		for (e = s; *e; ++e) {
-			if (*e == ' ')
-				break;
-		}
-
-		for (; s < e; ++s) {
-			putc (*s);
-		}
-	}
-
-
-	putc ('\n');
-
-	return (0);
-}
-
-
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-/*
-  initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
-  the necessary info for SDRAM controller configuration
-*/
-/* ------------------------------------------------------------------------- */
-/* ------------------------------------------------------------------------- */
-phys_size_t initdram (int board_type)
-{
-#ifndef CONFIG_ERIC
-	int i;
-	unsigned char datain[128];
-	int TotalSize;
-#endif
-
-	/*
-	 * ToDo: Move the asm init routine sdram_init() to this C file,
-	 * or even better use some common ppc4xx code available
-	 * in arch/powerpc/cpu/ppc4xx
-	 */
-	sdram_init();
-
-#ifdef CONFIG_ERIC
-	/*
-	 * we have no EEPROM on ERIC
-	 * so let init.S do the init job for SDRAM
-	 * and simply return 32MByte here
-	 */
-	return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
-#else
-
-	/* Read Serial Presence Detect Information */
-	for (i = 0; i < 128; i++)
-		datain[i] = 127;
-	i2c_send (SPD_EEPROM_ADDRESS, 0, 1, datain, 128);
-	printf ("\nReading DIMM...\n");
-#if 0
-	for (i = 0; i < 128; i++) {
-		printf ("%d=0x%x ", i, datain[i]);
-		if (((i + 1) % 10) == 0)
-			printf ("\n");
-	}
-	printf ("\n");
-#endif
-
-  /*****************************/
-	/* Retrieve interesting data */
-  /*****************************/
-	/* size of a SDRAM bank */
-	/* Number of bytes per side / number of banks per side */
-	if (datain[31] == 0x08)
-		TotalSize = 32;
-	else if (datain[31] == 0x10)
-		TotalSize = 64;
-	else {
-		printf ("IIC READ ERROR!!!\n");
-		TotalSize = 32;
-	}
-
-	/* single-sided DIMM or double-sided DIMM? */
-	if (datain[5] != 1) {
-		/* double-sided DIMM => SDRAM banks 0..3 are valid */
-		printf ("double-sided DIMM\n");
-		TotalSize *= 2;
-	}
-	/* else single-sided DIMM => SDRAM bank 0 and bank 2 are valid */
-	else {
-		printf ("single-sided DIMM\n");
-	}
-
-
-	/* return size in Mb unit => *(1024*1024) */
-	return (TotalSize * 1024 * 1024);
-#endif
-}
-
-/* ------------------------------------------------------------------------- */
-
-int testdram (void)
-{
-	/* TODO: XXX XXX XXX */
-	printf ("test: xxx MB - ok\n");
-
-	return (0);
-}
-
-/* ------------------------------------------------------------------------- */
diff --git a/board/eric/eric.h b/board/eric/eric.h
deleted file mode 100644
index b50d521..0000000
--- a/board/eric/eric.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- *                          Start Address    Length
- * +-----------------------+ 0x4000_0000     Start of Flash -----------------
- * | MON8xx code           | 0x4000_0100     Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused)              |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses    |                 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) |                 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address          |                 0x04
- * +-----------------------+ 0x4001_FFC0                     ^
- * | Hardware Information  |                 0x40            | MON8xx
- * +=======================+ 0x4002_0000 (sector border)    -----------------
- * | Autostart Header      |                                 | Applications
- * | ...                   |                                 v
- *
- *****************************************************************************/
diff --git a/board/eric/flash.c b/board/eric/flash.c
deleted file mode 100644
index 7459873..0000000
--- a/board/eric/flash.c
+++ /dev/null
@@ -1,1131 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
-
-
-#ifdef CONFIG_SYS_FLASH_16BIT
-#define FLASH_WORD_SIZE	unsigned short
-#define	FLASH_ID_MASK	0xFFFF
-#else
-#define FLASH_WORD_SIZE unsigned long
-#define	FLASH_ID_MASK	0xFFFFFFFF
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-/* stolen from esteem192e/flash.c */
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-#else
-static int write_short (flash_info_t *info, ulong dest, ushort data);
-#endif
-static void flash_get_offsets (ulong base, flash_info_t *info);
-
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	unsigned long size_b0, size_b1;
-	int i;
-	uint pbcr;
-	unsigned long base_b0, base_b1;
-
-	/* Init: no FLASHes known */
-	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0<<20);
-	}
-
-	/* Only one bank */
-	if (CONFIG_SYS_MAX_FLASH_BANKS == 1)
-	  {
-	    /* Setup offsets */
-	    flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
-
-	    /* Monitor protection ON by default */
-#if 0	    /* sand: */
-	    (void)flash_protect(FLAG_PROTECT_SET,
-				FLASH_BASE0_PRELIM-monitor_flash_len+size_b0,
-				FLASH_BASE0_PRELIM-1+size_b0,
-				&flash_info[0]);
-#else
-	    (void)flash_protect(FLAG_PROTECT_SET,
-				CONFIG_SYS_MONITOR_BASE,
-				CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-				&flash_info[0]);
-#endif
-	    size_b1 = 0 ;
-	    flash_info[0].size = size_b0;
-	  }
-
-	/* 2 banks */
-	else
-	  {
-	    size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)FLASH_BASE1_PRELIM, &flash_info[1]);
-
-	    /* Re-do sizing to get full correct info */
-
-	    if (size_b1)
-	      {
-		mtdcr(EBC0_CFGADDR, PB0CR);
-		pbcr = mfdcr(EBC0_CFGDATA);
-		mtdcr(EBC0_CFGADDR, PB0CR);
-		base_b1 = -size_b1;
-		pbcr = (pbcr & 0x0001ffff) | base_b1 | (((size_b1/1024/1024)-1)<<17);
-		mtdcr(EBC0_CFGDATA, pbcr);
-		/*          printf("PB1CR = %x\n", pbcr); */
-	      }
-
-	    if (size_b0)
-	      {
-		mtdcr(EBC0_CFGADDR, PB1CR);
-		pbcr = mfdcr(EBC0_CFGDATA);
-		mtdcr(EBC0_CFGADDR, PB1CR);
-		base_b0 = base_b1 - size_b0;
-		pbcr = (pbcr & 0x0001ffff) | base_b0 | (((size_b0/1024/1024)-1)<<17);
-		mtdcr(EBC0_CFGDATA, pbcr);
-		/*            printf("PB0CR = %x\n", pbcr); */
-	      }
-
-	    size_b0 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b0, &flash_info[0]);
-
-	    flash_get_offsets (base_b0, &flash_info[0]);
-
-	    /* monitor protection ON by default */
-#if 0	    /* sand: */
-	    (void)flash_protect(FLAG_PROTECT_SET,
-				FLASH_BASE0_PRELIM-monitor_flash_len+size_b0,
-				FLASH_BASE0_PRELIM-1+size_b0,
-				&flash_info[0]);
-#else
-	    (void)flash_protect(FLAG_PROTECT_SET,
-				CONFIG_SYS_MONITOR_BASE,
-				CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
-				&flash_info[0]);
-#endif
-
-	    if (size_b1) {
-	      /* Re-do sizing to get full correct info */
-	      size_b1 = flash_get_size((volatile FLASH_WORD_SIZE *)base_b1, &flash_info[1]);
-
-	      flash_get_offsets (base_b1, &flash_info[1]);
-
-	      /* monitor protection ON by default */
-	      (void)flash_protect(FLAG_PROTECT_SET,
-				  base_b1+size_b1-monitor_flash_len,
-				  base_b1+size_b1-1,
-				  &flash_info[1]);
-	      /* monitor protection OFF by default (one is enough) */
-	      (void)flash_protect(FLAG_PROTECT_CLEAR,
-				  base_b0+size_b0-monitor_flash_len,
-				  base_b0+size_b0-1,
-				  &flash_info[0]);
-	    } else {
-	      flash_info[1].flash_id = FLASH_UNKNOWN;
-	      flash_info[1].sector_count = -1;
-	    }
-
-	    flash_info[0].size = size_b0;
-	    flash_info[1].size = size_b1;
-	  }/* else 2 banks */
-	return (size_b0 + size_b1);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-static void flash_get_offsets (ulong base, flash_info_t *info)
-{
-	int i;
-
-	/* set up sector start adress table */
-	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_28F320J3A ||
-	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F640J3A ||
-	    (info->flash_id & FLASH_TYPEMASK) == FLASH_28F128J3A) {
-	    for (i = 0; i < info->sector_count; i++) {
-		info->start[i] = base + (i * info->size/info->sector_count);
-	    }
-	} else if (info->flash_id & FLASH_BTYPE) {
-	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00008000;
-		info->start[3] = base + 0x0000C000;
-		info->start[4] = base + 0x00010000;
-		info->start[5] = base + 0x00014000;
-		info->start[6] = base + 0x00018000;
-		info->start[7] = base + 0x0001C000;
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x000E0000;
-		}
-	       }
-	     else {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00008000;
-		info->start[2] = base + 0x0000C000;
-		info->start[3] = base + 0x00010000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00020000) - 0x00060000;
-		}
-	       }
-#else
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00002000;
-		info->start[2] = base + 0x00004000;
-		info->start[3] = base + 0x00006000;
-		info->start[4] = base + 0x00008000;
-		info->start[5] = base + 0x0000A000;
-		info->start[6] = base + 0x0000C000;
-		info->start[7] = base + 0x0000E000;
-		for (i = 8; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00070000;
-		}
-	       }
-	     else {
-		/* set sector offsets for bottom boot block type	*/
-		info->start[0] = base + 0x00000000;
-		info->start[1] = base + 0x00004000;
-		info->start[2] = base + 0x00006000;
-		info->start[3] = base + 0x00008000;
-		for (i = 4; i < info->sector_count; i++) {
-			info->start[i] = base + (i * 0x00010000) - 0x00030000;
-		}
-	       }
-#endif
-	} else {
-		/* set sector offsets for top boot block type		*/
-		i = info->sector_count - 1;
-	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		info->start[i--] = base + info->size - 0x00014000;
-		info->start[i--] = base + info->size - 0x00018000;
-		info->start[i--] = base + info->size - 0x0001C000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-
-	       } else {
-
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x00010000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00020000;
-		}
-	       }
-#else
-		info->start[i--] = base + info->size - 0x00002000;
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		info->start[i--] = base + info->size - 0x0000A000;
-		info->start[i--] = base + info->size - 0x0000C000;
-		info->start[i--] = base + info->size - 0x0000E000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-
-	       } else {
-
-		info->start[i--] = base + info->size - 0x00004000;
-		info->start[i--] = base + info->size - 0x00006000;
-		info->start[i--] = base + info->size - 0x00008000;
-		for (; i >= 0; i--) {
-			info->start[i] = base + i * 0x00010000;
-		}
-	       }
-#endif
-	}
-
-
-}
-
-/*-----------------------------------------------------------------------
- */
-
-void flash_print_info  (flash_info_t *info)
-{
-	int i;
-	uchar *boottype;
-	uchar botboot[]=", bottom boot sect)\n";
-	uchar topboot[]=", top boot sector)\n";
-
-	if (info->flash_id == FLASH_UNKNOWN) {
-		printf ("missing or unknown FLASH type\n");
-		return;
-	}
-
-	switch (info->flash_id & FLASH_VENDMASK) {
-	case FLASH_MAN_AMD:	printf ("AMD ");		break;
-	case FLASH_MAN_FUJ:	printf ("FUJITSU ");		break;
-	case FLASH_MAN_SST:	printf ("SST ");		break;
-	case FLASH_MAN_STM:	printf ("STM ");		break;
-	case FLASH_MAN_INTEL:	printf ("INTEL ");		break;
-	default:		printf ("Unknown Vendor ");	break;
-	}
-
-	if (info->flash_id & 0x0001 ) {
-	boottype = botboot;
-	} else {
-	boottype = topboot;
-	}
-
-	switch (info->flash_id & FLASH_TYPEMASK) {
-	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit%s",boottype);
-				break;
-	case FLASH_AM400T:	printf ("AM29LV400T (4 Mbit%s",boottype);
-				break;
-	case FLASH_AM800B:	printf ("AM29LV800B (8 Mbit%s",boottype);
-				break;
-	case FLASH_AM800T:	printf ("AM29LV800T (8 Mbit%s",boottype);
-				break;
-	case FLASH_AM160B:	printf ("AM29LV160B (16 Mbit%s",boottype);
-				break;
-	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit%s",boottype);
-				break;
-	case FLASH_AM320B:	printf ("AM29LV320B (32 Mbit%s",boottype);
-				break;
-	case FLASH_AM320T:	printf ("AM29LV320T (32 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL800B:	printf ("INTEL28F800B (8 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL800T:	printf ("INTEL28F800T (8 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL160B:	printf ("INTEL28F160B (16 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL160T:	printf ("INTEL28F160T (16 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL320B:	printf ("INTEL28F320B (32 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL320T:	printf ("INTEL28F320T (32 Mbit%s",boottype);
-				break;
-
-#if 0 /* enable when devices are available */
-
-	case FLASH_INTEL640B:	printf ("INTEL28F640B (64 Mbit%s",boottype);
-				break;
-	case FLASH_INTEL640T:	printf ("INTEL28F640T (64 Mbit%s",boottype);
-				break;
-#endif
-	case FLASH_28F320J3A:	printf ("INTEL28F320J3A (32 Mbit%s",boottype);
-				break;
-	case FLASH_28F640J3A:	printf ("INTEL28F640J3A (64 Mbit%s",boottype);
-				break;
-	case FLASH_28F128J3A:	printf ("INTEL28F128J3A (128 Mbit%s",boottype);
-				break;
-
-	default:		printf ("Unknown Chip Type\n");
-				break;
-	}
-
-	printf ("  Size: %ld MB in %d Sectors\n",
-		info->size >> 20, info->sector_count);
-
-	printf ("  Sector Start Addresses:");
-	for (i=0; i<info->sector_count; ++i) {
-		if ((i % 5) == 0)
-			printf ("\n   ");
-		printf (" %08lX%s",
-			info->start[i],
-			info->protect[i] ? " (RO)" : "     "
-		);
-	}
-	printf ("\n");
-	return;
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-
-/*-----------------------------------------------------------------------
- */
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info)
-{
-	short i;
-	ulong base = (ulong)addr;
-	FLASH_WORD_SIZE value;
-
-	/* Write auto select command: read Manufacturer ID */
-
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-
-	/*
-	 * Note: if it is an AMD flash and the word at addr[0000]
-	 * is 0x00890089 this routine will think it is an Intel
-	 * flash device and may(most likely) cause trouble.
-	 */
-
-	addr[0x0000] = 0x00900090;
-	if(addr[0x0000] != 0x00890089){
-		addr[0x0555] = 0x00AA00AA;
-		addr[0x02AA] = 0x00550055;
-		addr[0x0555] = 0x00900090;
-#else
-
-	/*
-	 * Note: if it is an AMD flash and the word at addr[0000]
-	 * is 0x0089 this routine will think it is an Intel
-	 * flash device and may(most likely) cause trouble.
-	 */
-
-	addr[0x0000] = 0x0090;
-
-	if(addr[0x0000] != 0x0089){
-		addr[0x0555] = 0x00AA;
-		addr[0x02AA] = 0x0055;
-		addr[0x0555] = 0x0090;
-#endif
-	}
-	value = addr[0];
-
-	switch (value) {
-	case (AMD_MANUFACT & FLASH_ID_MASK):
-		info->flash_id = FLASH_MAN_AMD;
-		break;
-	case (FUJ_MANUFACT & FLASH_ID_MASK):
-		info->flash_id = FLASH_MAN_FUJ;
-		break;
-	case (STM_MANUFACT & FLASH_ID_MASK):
-		info->flash_id = FLASH_MAN_STM;
-		break;
-	case (SST_MANUFACT & FLASH_ID_MASK):
-		info->flash_id = FLASH_MAN_SST;
-		break;
-	case (INTEL_MANUFACT & FLASH_ID_MASK):
-		info->flash_id = FLASH_MAN_INTEL;
-		break;
-	default:
-		info->flash_id = FLASH_UNKNOWN;
-		info->sector_count = 0;
-		info->size = 0;
-		return (0);			/* no or unknown flash	*/
-
-	}
-
-	value = addr[1];			/* device ID		*/
-
-	switch (value) {
-
-	case (AMD_ID_LV400T & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM400T;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (AMD_ID_LV400B & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM400B;
-		info->sector_count = 11;
-		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
-
-	case (AMD_ID_LV800T & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM800T;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (AMD_ID_LV800B & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM800B;
-		info->sector_count = 19;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (AMD_ID_LV160T & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM160T;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case (AMD_ID_LV160B & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM160B;
-		info->sector_count = 35;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-#if 0	/* enable when device IDs are available */
-	case (AMD_ID_LV320T & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM320T;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case (AMD_ID_LV320B & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 67;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-#endif
-
-	case (INTEL_ID_28F800B3T & FLASH_ID_MASK):
-		info->flash_id += FLASH_INTEL800T;
-		info->sector_count = 23;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (INTEL_ID_28F800B3B & FLASH_ID_MASK):
-		info->flash_id += FLASH_INTEL800B;
-		info->sector_count = 23;
-		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
-
-	case (INTEL_ID_28F160B3T & FLASH_ID_MASK):
-		info->flash_id += FLASH_INTEL160T;
-		info->sector_count = 39;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case (INTEL_ID_28F160B3B & FLASH_ID_MASK):
-		info->flash_id += FLASH_INTEL160B;
-		info->sector_count = 39;
-		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
-
-	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
-		info->flash_id += FLASH_INTEL320T;
-		info->sector_count = 71;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 71;
-		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
-
-#if 0 /* enable when devices are available */
-	case (INTEL_ID_28F320B3T & FLASH_ID_MASK):
-		info->flash_id += FLASH_INTEL320T;
-		info->sector_count = 135;
-		info->size = 0x01000000;
-		break;				/* => 16 MB		*/
-
-	case (INTEL_ID_28F320B3B & FLASH_ID_MASK):
-		info->flash_id += FLASH_AM320B;
-		info->sector_count = 135;
-		info->size = 0x01000000;
-		break;				/* => 16 MB		*/
-#endif
-	case (INTEL_ID_28F320J3A & FLASH_ID_MASK):
-		info->flash_id += FLASH_28F320J3A;
-		info->sector_count = 32;
-		info->size = 0x00400000;
-		break;				/* => 32 MBit	*/
-	case (INTEL_ID_28F640J3A & FLASH_ID_MASK):
-		info->flash_id += FLASH_28F640J3A;
-		info->sector_count = 64;
-		info->size = 0x00800000;
-		break;				/* => 64 MBit	*/
-	case (INTEL_ID_28F128J3A & FLASH_ID_MASK):
-		info->flash_id += FLASH_28F128J3A;
-		info->sector_count = 128;
-		info->size = 0x01000000;
-		break;				/* => 128 MBit	*/
-
-	default:
-		/* FIXME*/
-		info->flash_id = FLASH_UNKNOWN;
-		return (0);			/* => no or unknown flash */
-	}
-
-	flash_get_offsets(base, info);
-
-	/* check for protected sectors */
-	for (i = 0; i < info->sector_count; i++) {
-		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
-		/* D0 = 1 if protected */
-		addr = (volatile FLASH_WORD_SIZE *)(info->start[i]);
-		info->protect[i] = addr[2] & 1;
-	}
-
-	/*
-	 * Prevent writes to uninitialized FLASH.
-	 */
-	if (info->flash_id != FLASH_UNKNOWN) {
-		addr = (volatile FLASH_WORD_SIZE *)info->start[0];
-		if( (info->flash_id & 0xFF00) == FLASH_MAN_INTEL){
-		   *addr = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
-		} else {
-		   *addr = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
-		}
-	}
-
-	return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int	flash_erase (flash_info_t *info, int s_first, int s_last)
-{
-
-	volatile FLASH_WORD_SIZE *addr=(volatile FLASH_WORD_SIZE*)(info->start[0]);
-	int flag, prot, sect, l_sect, barf;
-	ulong start, now, last;
-	int rcode = 0;
-
-	if ((s_first < 0) || (s_first > s_last)) {
-		if (info->flash_id == FLASH_UNKNOWN) {
-			printf ("- missing\n");
-		} else {
-			printf ("- no sectors to erase\n");
-		}
-		return 1;
-	}
-
-	if ((info->flash_id == FLASH_UNKNOWN) ||
-	    ((info->flash_id > FLASH_AMD_COMP) &&
-	     ( (info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL ) ) ){
-		printf ("Can't erase unknown flash type - aborted\n");
-		return 1;
-	}
-
-	prot = 0;
-	for (sect=s_first; sect<=s_last; ++sect) {
-		if (info->protect[sect]) {
-			prot++;
-		}
-	}
-
-	if (prot) {
-		printf ("- Warning: %d protected sectors will not be erased!\n",
-			prot);
-	} else {
-		printf ("\n");
-	}
-
-	l_sect = -1;
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts();
-    if(info->flash_id < FLASH_AMD_COMP) {
-#ifndef CONFIG_SYS_FLASH_16BIT
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-	addr[0x0555] = 0x00800080;
-	addr[0x0555] = 0x00AA00AA;
-	addr[0x02AA] = 0x00550055;
-#else
-	addr[0x0555] = 0x00AA;
-	addr[0x02AA] = 0x0055;
-	addr[0x0555] = 0x0080;
-	addr[0x0555] = 0x00AA;
-	addr[0x02AA] = 0x0055;
-#endif
-	/* Start erase on unprotected sectors */
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			addr = (volatile FLASH_WORD_SIZE *)(info->start[sect]);
-			addr[0] = (0x00300030 & FLASH_ID_MASK);
-			l_sect = sect;
-		}
-	}
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts();
-
-	/* wait at least 80us - let's wait 1 ms */
-	udelay (1000);
-
-	/*
-	 * We wait for the last triggered sector
-	 */
-	if (l_sect < 0)
-		goto DONE;
-
-	start = get_timer (0);
-	last  = start;
-	addr = (volatile FLASH_WORD_SIZE*)(info->start[l_sect]);
-	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
-			  (0x00800080&FLASH_ID_MASK)  )
-	{
-		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
-			printf ("Timeout\n");
-			return 1;
-		}
-		/* show that we're waiting */
-		if ((now - last) > 1000) {	/* every second */
-			serial_putc ('.');
-			last = now;
-		}
-	}
-
-DONE:
-	/* reset to read mode */
-	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (0x00F000F0 & FLASH_ID_MASK);	/* reset bank */
-    } else {
-
-
-	for (sect = s_first; sect<=s_last; sect++) {
-		if (info->protect[sect] == 0) {	/* not protected */
-			barf = 0;
-#ifndef CONFIG_SYS_FLASH_16BIT
-			addr = (vu_long*)(info->start[sect]);
-			addr[0] = 0x00200020;
-			addr[0] = 0x00D000D0;
-			while(!(addr[0] & 0x00800080));	/* wait for error or finish */
-			if( addr[0] & 0x003A003A) {	/* check for error */
-				barf = addr[0] & 0x003A0000;
-				if( barf ) {
-					barf >>=16;
-				} else {
-					barf = addr[0] & 0x0000003A;
-				}
-			}
-#else
-			addr = (vu_short*)(info->start[sect]);
-			addr[0] = 0x0020;
-			addr[0] = 0x00D0;
-			while(!(addr[0] & 0x0080));	/* wait for error or finish */
-			if( addr[0] & 0x003A)	/* check for error */
-				barf = addr[0] & 0x003A;
-#endif
-			if(barf) {
-				printf("\nFlash error in sector at %lx\n",(unsigned long)addr);
-				if(barf & 0x0002) printf("Block locked, not erased.\n");
-				if((barf & 0x0030) == 0x0030)
-					printf("Command Sequence error.\n");
-				if((barf & 0x0030) == 0x0020)
-					printf("Block Erase error.\n");
-				if(barf & 0x0008) printf("Vpp Low error.\n");
-				rcode = 1;
-			} else printf(".");
-			l_sect = sect;
-		}
-	addr = (volatile FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
-
-	}
-
-    }
-	printf (" done\n");
-	return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-
-/*flash_info_t *addr2info (ulong addr)
-{
-	flash_info_t *info;
-	int i;
-
-	for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
-		if ((addr >= info->start[0]) &&
-		    (addr < (info->start[0] + info->size)) ) {
-			return (info);
-		}
-	}
-
-	return (NULL);
-}
-*/
-/*-----------------------------------------------------------------------
- * Copy memory to flash.
- * Make sure all target addresses are within Flash bounds,
- * and no protected sectors are hit.
- * Returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * 4 - target range includes protected sectors
- * 8 - target address not in Flash memory
- */
-
-/*int flash_write (uchar *src, ulong addr, ulong cnt)
-{
-	int i;
-	ulong         end        = addr + cnt - 1;
-	flash_info_t *info_first = addr2info (addr);
-	flash_info_t *info_last  = addr2info (end );
-	flash_info_t *info;
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	if (!info_first || !info_last) {
-		return (8);
-	}
-
-	for (info = info_first; info <= info_last; ++info) {
-		ulong b_end = info->start[0] + info->size;*/	/* bank end addr */
-/*		short s_end = info->sector_count - 1;
-		for (i=0; i<info->sector_count; ++i) {
-			ulong e_addr = (i == s_end) ? b_end : info->start[i + 1];
-
-			if ((end >= info->start[i]) && (addr < e_addr) &&
-			    (info->protect[i] != 0) ) {
-				return (4);
-			}
-		}
-	}
-
-*/	/* finally write data to flash */
-/*	for (info = info_first; info <= info_last && cnt>0; ++info) {
-		ulong len;
-
-		len = info->start[0] + info->size - addr;
-		if (len > cnt)
-			len = cnt;
-		if ((i = write_buff(info, src, addr, len)) != 0) {
-			return (i);
-		}
-		cnt  -= len;
-		addr += len;
-		src  += len;
-	}
-	return (0);
-}
-*/
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
-#ifndef CONFIG_SYS_FLASH_16BIT
-	ulong cp, wp, data;
-	int l;
-#else
-	ulong cp, wp;
-	ushort data;
-#endif
-	int i, rc;
-
-#ifndef CONFIG_SYS_FLASH_16BIT
-
-
-	wp = (addr & ~3);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start bytes
-	 */
-	if ((l = addr - wp) != 0) {
-		data = 0;
-		for (i=0, cp=wp; i<l; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-		for (; i<4 && cnt>0; ++i) {
-			data = (data << 8) | *src++;
-			--cnt;
-			++cp;
-		}
-		for (; cnt==0 && i<4; ++i, ++cp) {
-			data = (data << 8) | (*(uchar *)cp);
-		}
-
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 4;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-	while (cnt >= 4) {
-		data = 0;
-		for (i=0; i<4; ++i) {
-			data = (data << 8) | *src++;
-		}
-		if ((rc = write_word(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 4;
-		cnt -= 4;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<4; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_word(info, wp, data));
-
-#else
-	wp = (addr & ~1);	/* get lower word aligned address */
-
-	/*
-	 * handle unaligned start byte
-	 */
-	if (addr - wp) {
-		data = 0;
-		data = (data << 8) | *src++;
-		--cnt;
-		if ((rc = write_short(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp += 2;
-	}
-
-	/*
-	 * handle word aligned part
-	 */
-/*	l = 0; used for debuging  */
-	while (cnt >= 2) {
-		data = 0;
-		for (i=0; i<2; ++i) {
-			data = (data << 8) | *src++;
-		}
-
-/*		if(!l){
-			printf("%x",data);
-			l = 1;
-		}  used for debuging */
-
-		if ((rc = write_short(info, wp, data)) != 0) {
-			return (rc);
-		}
-		wp  += 2;
-		cnt -= 2;
-	}
-
-	if (cnt == 0) {
-		return (0);
-	}
-
-	/*
-	 * handle unaligned tail bytes
-	 */
-	data = 0;
-	for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) {
-		data = (data << 8) | *src++;
-		--cnt;
-	}
-	for (; i<2; ++i, ++cp) {
-		data = (data << 8) | (*(uchar *)cp);
-	}
-
-	return (write_short(info, wp, data));
-
-
-#endif
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-#ifndef CONFIG_SYS_FLASH_16BIT
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
-	vu_long *addr = (vu_long *) (info->start[0]);
-	ulong start, barf;
-	int flag;
-
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_long *) dest) & data) != data) {
-		return (2);
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	if (info->flash_id > FLASH_AMD_COMP) {
-		/* AMD stuff */
-		addr[0x0555] = 0x00AA00AA;
-		addr[0x02AA] = 0x00550055;
-		addr[0x0555] = 0x00A000A0;
-	} else {
-		/* intel stuff */
-		*addr = 0x00400040;
-	}
-	*((vu_long *) dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-
-	if (info->flash_id > FLASH_AMD_COMP) {
-
-		while ((*((vu_long *) dest) & 0x00800080) !=
-		       (data & 0x00800080)) {
-			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-
-	} else {
-
-		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
-			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-
-			if (addr[0] & 0x003A003A) {	/* check for error */
-				barf = addr[0] & 0x003A0000;
-				if (barf) {
-					barf >>= 16;
-				} else {
-					barf = addr[0] & 0x0000003A;
-				}
-				printf ("\nFlash write error at address %lx\n",
-					(unsigned long) dest);
-				if (barf & 0x0002)
-					printf ("Block locked, not erased.\n");
-				if (barf & 0x0010)
-					printf ("Programming error.\n");
-				if (barf & 0x0008)
-					printf ("Vpp Low error.\n");
-				return (2);
-			}
-
-
-		}
-
-		return (0);
-
-	}
-
-#else
-
-static int write_short (flash_info_t * info, ulong dest, ushort data)
-{
-	vu_short *addr = (vu_short *) (info->start[0]);
-	ulong start, barf;
-	int flag;
-
-	/* Check if Flash is (sufficiently) erased */
-	if ((*((vu_short *) dest) & data) != data) {
-		return (2);
-	}
-
-	/* Disable interrupts which might cause a timeout here */
-	flag = disable_interrupts ();
-
-	if (info->flash_id < FLASH_AMD_COMP) {
-		/* AMD stuff */
-		addr[0x0555] = 0x00AA;
-		addr[0x02AA] = 0x0055;
-		addr[0x0555] = 0x00A0;
-	} else {
-		/* intel stuff */
-		*addr = 0x00D0;
-		*addr = 0x0040;
-	}
-	*((vu_short *) dest) = data;
-
-	/* re-enable interrupts if necessary */
-	if (flag)
-		enable_interrupts ();
-
-	/* data polling for D7 */
-	start = get_timer (0);
-
-	if (info->flash_id < FLASH_AMD_COMP) {
-		/* AMD stuff */
-		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
-			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
-				return (1);
-			}
-		}
-
-	} else {
-		/* intel stuff */
-		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
-			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-				return (1);
-		}
-
-		if (addr[0] & 0x003A) {	/* check for error */
-			barf = addr[0] & 0x003A;
-			printf ("\nFlash write error at address %lx\n",
-				(unsigned long) dest);
-			if (barf & 0x0002)
-				printf ("Block locked, not erased.\n");
-			if (barf & 0x0010)
-				printf ("Programming error.\n");
-			if (barf & 0x0008)
-				printf ("Vpp Low error.\n");
-			return (2);
-		}
-		*addr = 0x00B0;
-		*addr = 0x0070;
-		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
-			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
-				return (1);
-		}
-		*addr = 0x00FF;
-	}
-	return (0);
-}
-#endif
-/*-----------------------------------------------------------------------*/
diff --git a/board/eric/init.S b/board/eric/init.S
deleted file mode 100644
index 1902241..0000000
--- a/board/eric/init.S
+++ /dev/null
@@ -1,359 +0,0 @@
-/*------------------------------------------------------------------------------+ */
-/* */
-/*       This source code is dual-licensed.  You may use it under the terms */
-/*       of the GNU General Public License version 2, or under the license  */
-/*       below.                                                             */
-/*                                                                          */
-/*       This source code has been made available to you by IBM on an AS-IS */
-/*       basis.  Anyone receiving this source is licensed under IBM */
-/*       copyrights to use it in any way he or she deems fit, including */
-/*       copying it, modifying it, compiling it, and redistributing it either */
-/*       with or without modifications.  No license under IBM patents or */
-/*       patent applications is to be implied by the copyright license. */
-/* */
-/*       Any user of this software should understand that IBM cannot provide */
-/*       technical support for this software and will not be responsible for */
-/*       any consequences resulting from the use of this software. */
-/* */
-/*       Any person who transfers this source code or any derivative work */
-/*       must include the IBM copyright notice, this paragraph, and the */
-/*       preceding two paragraphs in the transferred software. */
-/* */
-/*       COPYRIGHT   I B M   CORPORATION 1995 */
-/*       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
-/*------------------------------------------------------------------------------- */
-
-/*----------------------------------------------------------------------------- */
-/* Function:     ext_bus_cntlr_init */
-/* Description:  Initializes the External Bus Controller for the external */
-/*		peripherals. IMPORTANT: For pass1 this code must run from */
-/*		cache since you can not reliably change a peripheral banks */
-/*		timing register (pbxap) while running code from that bank. */
-/*		For ex., since we are running from ROM on bank 0, we can NOT */
-/*		execute the code that modifies bank 0 timings from ROM, so */
-/*		we run it from cache. */
-/* */
-/*----------------------------------------------------------------------------- */
-#include <config.h>
-#include <asm/ppc4xx.h>
-
-#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
-	.globl	ext_bus_cntlr_init
-ext_bus_cntlr_init:
-	mflr    r4                      /* save link register */
-	bl      ..getAddr
-..getAddr:
-	mflr    r3                      /* get address of ..getAddr */
-	mtlr    r4                      /* restore link register */
-	addi    r4,0,14                 /* set ctr to 10; used to prefetch */
-	mtctr   r4                      /* 10 cache lines to fit this function */
-					/* in cache (gives us 8x10=80 instrctns) */
-..ebcloop:
-	icbt    r0,r3                   /* prefetch cache line for addr in r3 */
-	addi    r3,r3,32		/* move to next cache line */
-	bdnz    ..ebcloop               /* continue for 10 cache lines */
-
-	/*------------------------------------------------------------------- */
-	/* Delay to ensure all accesses to ROM are complete before changing */
-	/* bank 0 timings. 200usec should be enough. */
-	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
-	/*------------------------------------------------------------------- */
-	addis	r3,0,0x0
-	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
-	mtctr   r3
-..spinlp:
-	bdnz    ..spinlp                /* spin loop */
-
-	/*----------------------------------------------------------------------- */
-	/* Memory Bank 0 (Flash) initialization (from openbios) */
-	/*----------------------------------------------------------------------- */
-
-	addi    r4,0,PB1AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS0_AP@h
-	ori     r4,r4,CS0_AP@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB0CR
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS0_CR@h
-	ori     r4,r4,CS0_CR@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	/*----------------------------------------------------------------------- */
-	/* Memory Bank 1 (NVRAM/RTC) initialization */
-	/*----------------------------------------------------------------------- */
-
-	addi    r4,0,PB1AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS1_AP@h
-	ori     r4,r4,CS1_AP@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB1CR
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS1_CR@h
-	ori     r4,r4,CS1_CR@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	/*----------------------------------------------------------------------- */
-	/* Memory Bank 2 (A/D converter) initialization */
-	/*----------------------------------------------------------------------- */
-
-	addi    r4,0,PB2AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS2_AP@h
-	ori     r4,r4,CS2_AP@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB2CR
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS2_CR@h
-	ori     r4,r4,CS2_CR@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	/*----------------------------------------------------------------------- */
-	/* Memory Bank 3 (Ethernet PHY Reset) initialization */
-	/*----------------------------------------------------------------------- */
-
-	addi    r4,0,PB3AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS3_AP@h
-	ori     r4,r4,CS3_AP@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB3CR
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS3_CR@h
-	ori     r4,r4,CS3_CR@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	/*----------------------------------------------------------------------- */
-	/* Memory Bank 4 (PC-MIP PRSNT1#) initialization */
-	/*----------------------------------------------------------------------- */
-
-	addi    r4,0,PB4AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS4_AP@h
-	ori     r4,r4,CS4_AP@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB4CR
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS4_CR@h
-	ori     r4,r4,CS4_CR@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	/*----------------------------------------------------------------------- */
-	/* Memory Bank 5 (PC-MIP PRSNT2#) initialization */
-	/*----------------------------------------------------------------------- */
-
-	addi    r4,0,PB5AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS5_AP@h
-	ori     r4,r4,CS5_AP@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB5CR
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS5_CR@h
-	ori     r4,r4,CS5_CR@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	/*----------------------------------------------------------------------- */
-	/* Memory Bank 6 (CPU LED0) initialization */
-	/*----------------------------------------------------------------------- */
-
-	addi    r4,0,PB6AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS6_AP@h
-	ori     r4,r4,CS6_AP@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB6CR
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS6_CR@h
-	ori     r4,r4,CS5_CR@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	/*----------------------------------------------------------------------- */
-	/* Memory Bank 7 (CPU LED1) initialization */
-	/*----------------------------------------------------------------------- */
-
-	addi    r4,0,PB7AP
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS7_AP@h
-	ori     r4,r4,CS7_AP@l
-	mtdcr   EBC0_CFGDATA,r4
-
-	addi    r4,0,PB7CR
-	mtdcr   EBC0_CFGADDR,r4
-	addis   r4,0,CS7_CR@h
-	ori     r4,r4,CS7_CR@l
-	mtdcr   EBC0_CFGDATA,r4
-
-/*	addis   r4,r0,FPGA_BRDC@h */
-/*	ori     r4,r4,FPGA_BRDC@l */
-/*	lbz     r3,0(r4)                /###*get FPGA board control reg */
-/*	eieio */
-/*	ori	r3,r3,0x01              /###*set UART1 control to select CTS/RTS */
-/*	stb     r3,0(r4) */
-
-	nop				/* pass2 DCR errata #8 */
-	blr
-
-/*----------------------------------------------------------------------------- */
-/* Function:     sdram_init */
-/* Description:  Configures SDRAM memory banks on ERIC. */
-/*               We do manually init our SDRAM. */
-/*               If we have two SDRAM banks, simply undef SINGLE_BANK (ROLF :-) */
-/*		 It is assumed that a 32MB 12x8(2) SDRAM is used. */
-/*----------------------------------------------------------------------------- */
-	.globl  sdram_init
-
-sdram_init:
-
-	mflr	r31
-
-#ifdef CONFIG_SYS_SDRAM_MANUALLY
-	/*------------------------------------------------------------------- */
-	/* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
-	/*------------------------------------------------------------------- */
-
-	addi    r4,0,SDRAM0_B0CR
-	mtdcr   SDRAM0_CFGADDR,r4
-	addis   r4,0,MB0CF@h
-	ori     r4,r4,MB0CF@l
-	mtdcr   SDRAM0_CFGDATA,r4
-
-	/*------------------------------------------------------------------- */
-	/* Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2) */
-	/*------------------------------------------------------------------- */
-
-	addi    r4,0,SDRAM0_B1CR
-	mtdcr   SDRAM0_CFGADDR,r4
-	addis   r4,0,MB1CF@h
-	ori     r4,r4,MB1CF@l
-	mtdcr   SDRAM0_CFGDATA,r4
-
-	/*------------------------------------------------------------------- */
-	/* Set MB2CF for bank 2. off */
-	/*------------------------------------------------------------------- */
-
-	addi    r4,0,SDRAM0_B2CR
-	mtdcr   SDRAM0_CFGADDR,r4
-	addis   r4,0,MB2CF@h
-	ori     r4,r4,MB2CF@l
-	mtdcr   SDRAM0_CFGDATA,r4
-
-	/*------------------------------------------------------------------- */
-	/* Set MB3CF for bank 3. off */
-	/*------------------------------------------------------------------- */
-
-	addi    r4,0,SDRAM0_B3CR
-	mtdcr   SDRAM0_CFGADDR,r4
-	addis   r4,0,MB3CF@h
-	ori     r4,r4,MB3CF@l
-	mtdcr   SDRAM0_CFGDATA,r4
-
-	/*------------------------------------------------------------------- */
-	/* Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. */
-	/* To set the appropriate timings, we need to know the SDRAM speed. */
-	/* We can use the PLB speed since the SDRAM speed is the same as */
-	/* the PLB speed. The PLB speed is the FBK divider times the */
-	/* 405GP reference clock, which on the Walnut board is 33Mhz. */
-	/* Thus, if FBK div is 2, SDRAM is 66Mhz; if FBK div is 3, SDRAM is */
-	/* 100Mhz; if FBK is 3, SDRAM is 133Mhz. */
-	/* NOTE: The Walnut board supports SDRAM speeds of 66Mhz, 100Mhz, and */
-	/* maybe 133Mhz. */
-	/*------------------------------------------------------------------- */
-
-	mfdcr   r5,CPC0_PSR               /* determine FBK divider */
-					  /* via STRAP reg to calc PLB speed. */
-					  /* SDRAM speed is the same as the PLB */
-					  /* speed. */
-	rlwinm  r4,r5,4,0x3             /* get FBK divide bits */
-
-..chk_66:
-	cmpi    %cr0,0,r4,0x1
-	bne     ..chk_100
-	addis	r6,0,SDTR_66@h		/* SDTR1 value for 66Mhz */
-	ori     r6,r6,SDTR_66@l
-	addis	r7,0,RTR_66		/* RTR value for 66Mhz */
-	b	..sdram_ok
-..chk_100:
-	cmpi    %cr0,0,r4,0x2
-	bne     ..chk_133
-	addis   r6,0,SDTR_100@h        /* SDTR1 value for 100Mhz */
-	ori     r6,r6,SDTR_100@l
-	addis   r7,0,RTR_100           /* RTR value for 100Mhz */
-	b       ..sdram_ok
-..chk_133:
-	addis   r6,0,0x0107            /* SDTR1 value for 133Mhz */
-	ori     r6,r6,0x4015
-	addis   r7,0,0x07F0            /* RTR value for 133Mhz */
-
-..sdram_ok:
-	/*------------------------------------------------------------------- */
-	/* Set SDTR1 */
-	/*------------------------------------------------------------------- */
-	addi    r4,0,SDRAM0_TR
-	mtdcr   SDRAM0_CFGADDR,r4
-	mtdcr   SDRAM0_CFGDATA,r6
-
-	/*------------------------------------------------------------------- */
-	/* Set RTR */
-	/*------------------------------------------------------------------- */
-	addi    r4,0,SDRAM0_RTR
-	mtdcr   SDRAM0_CFGADDR,r4
-	mtdcr   SDRAM0_CFGDATA,r7
-
-	/*------------------------------------------------------------------- */
-	/* Delay to ensure 200usec have elapsed since reset. Assume worst */
-	/* case that the core is running 200Mhz: */
-	/*   200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
-	/*------------------------------------------------------------------- */
-	addis   r3,0,0x0000
-	ori     r3,r3,0xA000          /* ensure 200usec have passed since reset */
-	mtctr   r3
-..spinlp2:
-	bdnz    ..spinlp2               /* spin loop */
-
-	/*------------------------------------------------------------------- */
-	/* Set memory controller options reg, MCOPT1. */
-	/* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */
-	/* read/prefetch. */
-	/*------------------------------------------------------------------- */
-	addi    r4,0,SDRAM0_CFG
-	mtdcr   SDRAM0_CFGADDR,r4
-	addis   r4,0,0x8080             /* set DC_EN=1 */
-	ori     r4,r4,0x0000
-	mtdcr   SDRAM0_CFGDATA,r4
-
-	/*------------------------------------------------------------------- */
-	/* Delay to ensure 10msec have elapsed since reset. This is */
-	/* required for the MPC952 to stabalize. Assume worst */
-	/* case that the core is running 200Mhz: */
-	/*   200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */
-	/* This delay should occur before accessing SDRAM. */
-	/*------------------------------------------------------------------- */
-	addis   r3,0,0x001E
-	ori     r3,r3,0x8480          /* ensure 10msec have passed since reset */
-	mtctr   r3
-..spinlp3:
-	bdnz    ..spinlp3                /* spin loop */
-
-#else
-/*fixme: do SDRAM Autoconfig from EEPROM here */
-
-#endif
-	mtlr    r31                     /* restore lr */
-	blr
diff --git a/boards.cfg b/boards.cfg
index a37ccc5..a4825f7 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -269,7 +269,6 @@ TTTech		powerpc	mpc8xx		tqm8xx		tqc		-	TQM823L:LCD,SHARP_LQ104V7DS01
 wtk		powerpc	mpc8xx		tqm8xx		tqc		-	TQM823L:LCD,SHARP_LQ065T9DR51U
 csb272		powerpc	ppc4xx
 csb472		powerpc	ppc4xx
-ERIC		powerpc	ppc4xx		eric
 G2000		powerpc	ppc4xx		g2000
 JSE		powerpc	ppc4xx		jse
 korat		powerpc	ppc4xx
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 4286559..fd2b726 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,7 +11,8 @@ easily if here is something they might want to dig for...
 
 Board	Arch	CPU	removed	    Commit	last known maintainer/contact
 =============================================================================
-VoVPN-GW_100MHz	powerpc	MPC8260 - 2010-10-24	Juergen Selent <j.selent@elmeg.de>
+ERIC	powerpc	405GP	-	  2010-11-21	Swen Anderson <sand@peppercon.de>
+VoVPN-GW_100MHz	powerpc	MPC8260 26fe3d2 2010-10-24	Juergen Selent <j.selent@elmeg.de>
 NC650	powerpc	MPC852	333d86d   2010-10-19	Wolfgang Denk <wd@denx.de>
 CP850	powerpc	MPC852	333d86d   2010-10-19	Wolfgang Denk <wd@denx.de>
 logodl	ARM	PXA2xx	059e778   2010-10-18	August Hoeraendl <august.hoerandl@gmx.at>
diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h
deleted file mode 100644
index 8a0f850..0000000
--- a/include/configs/ERIC.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
-#define CONFIG_ERIC		1	/* ...on a ERIC board	*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000
-
-#define	CONFIG_BOARD_EARLY_INIT_F 1	/* run board_early_init_f() */
-
-#define CONFIG_SYS_CLK_FREQ	33333333 /* external frequency to pll	*/
-
-#if 1
-#define CONFIG_ENV_IS_IN_FLASH	1	/* use FLASH for environment vars	*/
-#endif
-#if 0
-#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#endif
-#if 0
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use I2C RTC X1240 for environment vars */
-#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x800	/* 2048 bytes may be used for env vars */
-#endif					/* total size of a X1240 is 2048 bytes */
-
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
-#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57	/* X1240 has two I2C slave addresses, one for EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* address length for the eeprom */
-#define CONFIG_I2C_RTC		1	/* we have a Xicor X1240 RTC */
-#define CONFIG_SYS_I2C_RTC_ADDR	0x6F	/*                                and one for RTC */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_EEPROM
-#else
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_EEPROM
-#else
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#endif
-#endif
-#endif
-
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#if 1
-#define CONFIG_BOOTCOMMAND	"bootm ffc00000" /* autoboot command	*/
-#else
-#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/
-#endif
-
-#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/nfs "	\
-				"nfsroot=192.168.1.2:/eric_root_devel "	\
-				"ip=192.168.1.22:192.168.1.2"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		1	/* PHY address			*/
-#define CONFIG_NET_MULTI
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_SAVEENV
-#define CONFIG_CMD_FLASH
-
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#undef	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#define	 CONFIG_SYS_EXT_SERIAL_CLOCK	 14318180
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO		1	/* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
-#define PCI_HOST_FORCE  1               /* configure as pci host        */
-#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
-
-#define CONFIG_PCI			/* include pci support	        */
-#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function     */
-#undef  CONFIG_PCI_PNP			/* no pci plug-and-play         */
-					/* resource configuration       */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1743	/* PCI Vendor ID: Peppercon AG	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405	/* PCI Device ID: 405GP		*/
-#define CONFIG_SYS_PCI_PTM1LA	0xFFFC0000	/* point to flash		*/
-#define CONFIG_SYS_PCI_PTM1MS	0xFFFFF001	/* 4kB, enable hard-wired to 1	*/
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
-#define CONFIG_SYS_PCI_PTM2LA	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2MS	0x00000000	/* disabled			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
-
-/*-----------------------------------------------------------------------
- * External peripheral base address
- *-----------------------------------------------------------------------
- */
-/*	Bank 0 - Flash/SRAM	       0xFF000000 16MB	16 Bit */
-/*	Bank 1 - NVRAM/RTC	       0xF0000000  1MB	 8 Bit */
-/*	Bank 2 - A/D converter	       0xF0100000  1MB	 8 Bit */
-/*	Bank 3 - Ethernet PHY Reset    0xF0200000  1MB	 8 Bit */
-/*	Bank 4 - PC-MIP PRSNT1#	       0xF0300000  1MB	 8 Bit */
-/*	Bank 5 - PC-MIP PRSNT2#	       0xF0400000  1MB	 8 Bit */
-/*	Bank 6 - CPU LED0	       0xF0500000  1MB	 8 Bit */
-/*	Bank 7 - CPU LED1	       0xF0600000  1MB	 8 Bit */
-
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 0 (Flash) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS0_AP	0x9B015480
-#define CS0_CR	0xFF87A000 /*  BAS=0xFF8,BS=(8MB),BU=0x3(R/W), BW=(16 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 1 (NVRAM/RTC) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS1_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS1_CR	0xF0018000 /* BAS=0xF00,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
- /* ----------------------------------------------------------------------- */
- /*  Memory Bank 2 (A/D converter) initialization */
- /* ----------------------------------------------------------------------- */
-#define CS2_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS2_CR	0xF0118000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 3 (Ethernet PHY Reset) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS3_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS3_CR	0xF0218000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 4 (PC-MIP PRSNT1#) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS4_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS4_CR	0xF0318000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 5 (PC-MIP PRSNT2#) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS5_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS5_CR	0xF0418000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 6 (CPU LED0) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS6_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS6_CR	0xF0518000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-/* ----------------------------------------------------------------------- */
-/*  Memory Bank 7 (CPU LED1) initialization */
-/* ----------------------------------------------------------------------- */
-#define CS7_AP	0x02815480 /* WT=1, OEN=0x1,WBN=0x1,WBF=0x1,TH=0x2,RE=0, */
-#define CS7_CR	0xF0618000 /* BAS=0xF01,BS=(1MB),BU=0x3(R/W), BW=(8 bits) */
-
-#define CONFIG_SYS_NVRAM_REG_BASE_ADDR	 0xF0000000
-#define CONFIG_SYS_RTC_REG_BASE_ADDR	 (0xF0000000 + 0x7F8)
-#define CONFIG_SYS_ADC_REG_BASE_ADDR	 0xF0100000
-#define CONFIG_SYS_PHYRES_REG_BASE_ADDR 0xF0200000
-#define CONFIG_SYS_PRSNT1_REG_BASE_ADDR 0xF0300000
-#define CONFIG_SYS_PRSNT2_REG_BASE_ADDR 0xF0400000
-#define CONFIG_SYS_LED0_REG_BASE_ADDR	 0xF0500000
-#define CONFIG_SYS_LED1_REG_BASE_ADDR	 0xF0600000
-
-
-/*  SDRAM CONFIG */
-#define CONFIG_SYS_SDRAM_MANUALLY    1
-#define CONFIG_SYS_SDRAM_SINGLE_BANK 1
-
-#ifdef CONFIG_SYS_SDRAM_MANUALLY
-/*-----------------------------------------------------------------------
- * Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2)
- *----------------------------------------------------------------------*/
-#define MB0CF	0x00062001 /*  32MB @ 0 */
-/*-----------------------------------------------------------------------
- * Set MB1CF for bank 1. (32MB-64MB) Address Mode 4 since 12x8(2)
- *----------------------------------------------------------------------*/
-#ifdef CONFIG_SYS_SDRAM_SINGLE_BANK
-#define MB1CF	0x0 /*  0MB @ 32MB */
-#else
-#define MB1CF	0x02062001 /*  32MB @ 32MB */
-#endif
-/*-----------------------------------------------------------------------
- * Set MB2CF for bank 2. off
- *----------------------------------------------------------------------*/
-#define MB2CF	0x0 /*  0MB */
-/*-----------------------------------------------------------------------
- * Set MB3CF for bank 3. off
- *----------------------------------------------------------------------*/
-#define MB3CF	0x0 /*  0MB */
-
-#define SDTR_100    0x0086400D
-#define RTR_100     0x05F0
-#define SDTR_66     0x00854006	/* orig U-Boot-wallnut says 0x00854006 */
-#define RTR_66      0x03f8
-
-#endif   /* CONFIG_SYS_SDRAM_MANUALLY */
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_SDRAM_SIZE		32
-#define CONFIG_SYS_FLASH_BASE		0xFF800000      /* 8 MByte Flash */
-#define CONFIG_SYS_MONITOR_BASE	0xFFFE0000      /* last 128kByte within Flash */
-/*#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)*/	/* Reserve 196 kB for Monitor	*/
-#define CONFIG_SYS_MONITOR_LEN		(128 * 1024)	/* Reserve 128 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/
-#define CONFIG_SYS_FLASH_16BIT		1	/* Rom 16 bit data bus			*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE       (128*1024)
-
-#if 0  /* force ENV to be NOT embedded */
-#define CONFIG_ENV_ADDR            0xfffa0000
-#else  /* force ENV to be embedded */
-#define	CONFIG_ENV_SIZE		(2 * 1024) /* Total Size of Environment Sector 2k */
-#define CONFIG_ENV_ADDR            (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SIZE - 0x10) /* let space for reset vector */
-/* #define CONFIG_ENV_ADDR            (CONFIG_SYS_MONITOR_BASE)*/
-#define CONFIG_ENV_OFFSET          (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#endif
-
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR	CONFIG_SYS_NVRAM_REG_BASE_ADDR	/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		0x7F8		/* NVRAM size 2kByte - 8 Byte for RTC */
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE		0x7F8		/* Size of Environment vars	*/
-#define CONFIG_ENV_ADDR		\
-	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0 8MB	*/
-#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/
-
-
-/* Configuration Port location */
-/*  #define CONFIG_PORT_ADDR	0xF0000500 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x00df0000  /* inside of SDRAM		       */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x0f00	/* Size of used area in RAM	       */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS      0x50
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
-#endif
-#endif	/* __CONFIG_H */
