From patchwork Thu Nov 25 07:35:50 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 73037 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CCA5BB7043 for ; Thu, 25 Nov 2010 20:05:57 +1100 (EST) Received: from localhost ([127.0.0.1]:52438 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PLXG4-00028u-J0 for incoming@patchwork.ozlabs.org; Thu, 25 Nov 2010 03:32:48 -0500 Received: from [140.186.70.92] (port=44237 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PLWNA-0007KW-8M for qemu-devel@nongnu.org; Thu, 25 Nov 2010 02:36:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PLWN4-00020i-Jg for qemu-devel@nongnu.org; Thu, 25 Nov 2010 02:36:04 -0500 Received: from cantor2.suse.de ([195.135.220.15]:56291 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PLWN4-0001zp-9K for qemu-devel@nongnu.org; Thu, 25 Nov 2010 02:35:58 -0500 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) by mx2.suse.de (Postfix) with ESMTP id 6B42087567; Thu, 25 Nov 2010 08:35:56 +0100 (CET) From: Alexander Graf To: QEMU-devel Developers Date: Thu, 25 Nov 2010 08:35:50 +0100 Message-Id: <1290670555-12575-11-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1290670555-12575-1-git-send-email-agraf@suse.de> References: <1290670555-12575-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 Cc: Blue Swirl , Paul Brook Subject: [Qemu-devel] [PATCH 10/15] ppc4xx_pci: Declare as little endian X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch replaces explicit bswaps with endianness hints to the mmio layer. Signed-off-by: Alexander Graf --- hw/ppc4xx_pci.c | 17 ++--------------- 1 files changed, 2 insertions(+), 15 deletions(-) diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c index f2ecece..f62f1f9 100644 --- a/hw/ppc4xx_pci.c +++ b/hw/ppc4xx_pci.c @@ -24,7 +24,6 @@ #include "ppc4xx.h" #include "pci.h" #include "pci_host.h" -#include "bswap.h" #undef DEBUG #ifdef DEBUG @@ -102,10 +101,6 @@ static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr, { PPC4xxPCIState *ppc4xx_pci = opaque; -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif - ppc4xx_pci->pci_state.config_reg = value & ~0x3; } @@ -120,10 +115,6 @@ static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, { struct PPC4xxPCIState *pci = opaque; -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif - /* We ignore all target attempts at PCI configuration, effectively * assuming a bidirectional 1:1 mapping of PLB and PCI space. */ @@ -251,10 +242,6 @@ static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset) value = 0; } -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif - return value; } @@ -373,7 +360,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], /* CFGADDR */ index = cpu_register_io_memory(pci4xx_cfgaddr_read, pci4xx_cfgaddr_write, controller, - DEVICE_NATIVE_ENDIAN); + DEVICE_LITTLE_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); @@ -386,7 +373,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], /* Internal registers */ index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller, - DEVICE_NATIVE_ENDIAN); + DEVICE_LITTLE_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(registers, PCI_REG_SIZE, index);