@@ -6,20 +6,14 @@
* Common bits between 4K and 64K pages in a linux-style PTE.
* Additional bits may be defined in pgtable-hash64-*.h
*
- * Note: We only support user read/write permissions. Supervisor always
- * have full read/write to pages above PAGE_OFFSET (pages below that
- * always use the user access permissions).
- *
- * We could create separate kernel read-only if we used the 3 PP bits
- * combinations that newer processors provide but we currently don't.
*/
-#define H_PAGE_BUSY _RPAGE_SW1 /* software: PTE & hash are busy */
+#define H_PAGE_BUSY _RPAGE_RPN45 /* software: PTE & hash are busy */
#define H_PTE_NONE_MASK _PAGE_HPTEFLAGS
-#define H_PAGE_F_GIX_SHIFT 57
-/* (7ul << 57) HPTE index within HPTEG */
-#define H_PAGE_F_GIX (_RPAGE_RSV2 | _RPAGE_RSV3 | _RPAGE_RSV4)
-#define H_PAGE_F_SECOND _RPAGE_RSV1 /* HPTE is in 2ndary HPTEG */
-#define H_PAGE_HASHPTE _RPAGE_SW0 /* PTE has associated HPTE */
+#define H_PAGE_F_GIX_SHIFT 53
+/* (7ul << 53) HPTE index within HPTEG */
+#define H_PAGE_F_GIX (_RPAGE_RPN44 | _RPAGE_RPN43 | _RPAGE_RPN42)
+#define H_PAGE_F_SECOND _RPAGE_RPN41 /* HPTE is in 2ndary HPTEG */
+#define H_PAGE_HASHPTE _RPAGE_RPN40 /* PTE has associated HPTE */
/*
* Max physical address bit we will use for now.
*
@@ -30,16 +30,29 @@
#define _RPAGE_RSV2 0x0800000000000000UL
#define _RPAGE_RSV3 0x0400000000000000UL
#define _RPAGE_RSV4 0x0200000000000000UL
+
+#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
+#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
+
+/*
+ * Top and bottom bits of RPN which can be used by hash
+ * translation mode, because we expect them to be zero
+ * otherwise.
+ */
#define _RPAGE_RPN0 0x01000
#define _RPAGE_RPN1 0x02000
+#define _RPAGE_RPN45 0x0100000000000000UL
+#define _RPAGE_RPN44 0x0080000000000000UL
+#define _RPAGE_RPN43 0x0040000000000000UL
+#define _RPAGE_RPN42 0x0020000000000000UL
+#define _RPAGE_RPN41 0x0010000000000000UL
+#define _RPAGE_RPN40 0x0008000000000000UL
+
/* Max physicall address bit as per radix table */
#define _RPAGE_PA_MAX 57
#define _PAGE_SOFT_DIRTY _RPAGE_SW3 /* software: software dirty tracking */
#define _PAGE_SPECIAL _RPAGE_SW2 /* software: special page */
-
-#define _PAGE_PTE 0x4000000000000000UL /* distinguishes PTEs from pointers */
-#define _PAGE_PRESENT 0x8000000000000000UL /* pte contains a translation */
/*
* Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
* Instead of fixing all of them, add an alternate define which
We don't support the full 57 bits of physical address and hence can overload the top bits of RPN as hash specific pte bits. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> --- arch/powerpc/include/asm/book3s/64/hash.h | 18 ++++++------------ arch/powerpc/include/asm/book3s/64/pgtable.h | 19 ++++++++++++++++--- 2 files changed, 22 insertions(+), 15 deletions(-)