From patchwork Thu Nov 25 07:35:48 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexander Graf X-Patchwork-Id: 73035 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 173CEB70A7 for ; Thu, 25 Nov 2010 20:01:22 +1100 (EST) Received: from localhost ([127.0.0.1]:51315 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PLXDL-00018O-FX for incoming@patchwork.ozlabs.org; Thu, 25 Nov 2010 03:29:59 -0500 Received: from [140.186.70.92] (port=44208 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PLWN8-0007Jv-T9 for qemu-devel@nongnu.org; Thu, 25 Nov 2010 02:36:09 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PLWN4-00020T-Id for qemu-devel@nongnu.org; Thu, 25 Nov 2010 02:36:02 -0500 Received: from cantor.suse.de ([195.135.220.2]:39399 helo=mx1.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PLWN4-0001zy-9H for qemu-devel@nongnu.org; Thu, 25 Nov 2010 02:35:58 -0500 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 645C294393; Thu, 25 Nov 2010 08:35:56 +0100 (CET) From: Alexander Graf To: QEMU-devel Developers Date: Thu, 25 Nov 2010 08:35:48 +0100 Message-Id: <1290670555-12575-9-git-send-email-agraf@suse.de> X-Mailer: git-send-email 1.6.0.2 In-Reply-To: <1290670555-12575-1-git-send-email-agraf@suse.de> References: <1290670555-12575-1-git-send-email-agraf@suse.de> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.4-2.6 Cc: Blue Swirl , Paul Brook Subject: [Qemu-devel] [PATCH 08/15] prep: Declare as little endian X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This patch replaces explicit bswaps with endianness hints to the mmio layer. Signed-off-by: Alexander Graf --- hw/ppc_prep.c | 38 +++----------------------------------- 1 files changed, 3 insertions(+), 35 deletions(-) diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 80f5db6..1492266 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -145,20 +145,12 @@ static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) { -#ifdef TARGET_WORDS_BIGENDIAN - return bswap16(_PPC_intack_read(addr)); -#else return _PPC_intack_read(addr); -#endif } static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) { -#ifdef TARGET_WORDS_BIGENDIAN - return bswap32(_PPC_intack_read(addr)); -#else return _PPC_intack_read(addr); -#endif } static CPUWriteMemoryFunc * const PPC_intack_write[] = { @@ -210,9 +202,6 @@ static void PPC_XCSR_writeb (void *opaque, static void PPC_XCSR_writew (void *opaque, target_phys_addr_t addr, uint32_t value) { -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap16(value); -#endif printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, value); } @@ -220,9 +209,6 @@ static void PPC_XCSR_writew (void *opaque, static void PPC_XCSR_writel (void *opaque, target_phys_addr_t addr, uint32_t value) { -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, value); } @@ -243,9 +229,6 @@ static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, retval); -#ifdef TARGET_WORDS_BIGENDIAN - retval = bswap16(retval); -#endif return retval; } @@ -256,9 +239,6 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr, retval); -#ifdef TARGET_WORDS_BIGENDIAN - retval = bswap32(retval); -#endif return retval; } @@ -484,9 +464,6 @@ static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, sysctrl_t *sysctrl = opaque; addr = prep_IO_address(sysctrl, addr); -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap16(value); -#endif PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); cpu_outw(addr, value); } @@ -498,9 +475,6 @@ static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) addr = prep_IO_address(sysctrl, addr); ret = cpu_inw(addr); -#ifdef TARGET_WORDS_BIGENDIAN - ret = bswap16(ret); -#endif PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); return ret; @@ -512,9 +486,6 @@ static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, sysctrl_t *sysctrl = opaque; addr = prep_IO_address(sysctrl, addr); -#ifdef TARGET_WORDS_BIGENDIAN - value = bswap32(value); -#endif PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value); cpu_outl(addr, value); } @@ -526,9 +497,6 @@ static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) addr = prep_IO_address(sysctrl, addr); ret = cpu_inl(addr); -#ifdef TARGET_WORDS_BIGENDIAN - ret = bswap32(ret); -#endif PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret); return ret; @@ -691,7 +659,7 @@ static void ppc_prep_init (ram_addr_t ram_size, /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, PPC_prep_io_write, sysctrl, - DEVICE_NATIVE_ENDIAN); + DEVICE_LITTLE_ENDIAN); cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); /* init basic PC hardware */ @@ -757,12 +725,12 @@ static void ppc_prep_init (ram_addr_t ram_size, /* PCI intack location */ PPC_io_memory = cpu_register_io_memory(PPC_intack_read, PPC_intack_write, NULL, - DEVICE_NATIVE_ENDIAN); + DEVICE_LITTLE_ENDIAN); cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); /* PowerPC control and status register group */ #if 0 PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write, - NULL, DEVICE_NATIVE_ENDIAN); + NULL, DEVICE_LITTLE_ENDIAN); cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); #endif