| Message ID | 1487563478-22265-2-git-send-email-sjitindarsingh@gmail.com |
|---|---|
| State | New |
| Headers | show |
On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh wrote: > POWER9 processors implement the mmu as defined in version 3.00 of the ISA. > > Add a definition for this mmu model and set the POWER9 cpu model to use > this mmu model. > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> > --- > target/ppc/cpu-qom.h | 5 ++++- > target/ppc/mmu_helper.c | 2 ++ > target/ppc/translate_init.c | 3 +-- > 3 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h > index b7977ba..4e3132b 100644 > --- a/target/ppc/cpu-qom.h > +++ b/target/ppc/cpu-qom.h > @@ -86,10 +86,13 @@ enum powerpc_mmu_t { > POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > | POWERPC_MMU_64K > | POWERPC_MMU_AMR | 0x00000004, > - /* FIXME Add POWERPC_MMU_3_OO defines */ > /* Architecture 2.07 "degraded" (no 1T segments) */ > POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR > | 0x00000004, > + /* Architecture 3.00 variant */ > + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > + | POWERPC_MMU_64K > + | POWERPC_MMU_AMR | 0x00000005, I wonder if we need a POWERPC_MMU_RADIX that we can then attach with future versions Balbir Singh.
On Mon, Feb 20, 2017 at 04:16:26PM +1100, Balbir Singh wrote: > On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh wrote: > > POWER9 processors implement the mmu as defined in version 3.00 of the ISA. > > > > Add a definition for this mmu model and set the POWER9 cpu model to use > > this mmu model. > > > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> > > --- > > target/ppc/cpu-qom.h | 5 ++++- > > target/ppc/mmu_helper.c | 2 ++ > > target/ppc/translate_init.c | 3 +-- > > 3 files changed, 7 insertions(+), 3 deletions(-) > > > > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h > > index b7977ba..4e3132b 100644 > > --- a/target/ppc/cpu-qom.h > > +++ b/target/ppc/cpu-qom.h > > @@ -86,10 +86,13 @@ enum powerpc_mmu_t { > > POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > > | POWERPC_MMU_64K > > | POWERPC_MMU_AMR | 0x00000004, > > - /* FIXME Add POWERPC_MMU_3_OO defines */ > > /* Architecture 2.07 "degraded" (no 1T segments) */ > > POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR > > | 0x00000004, > > + /* Architecture 3.00 variant */ > > + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > > + | POWERPC_MMU_64K > > + | POWERPC_MMU_AMR | 0x00000005, > > I wonder if we need a POWERPC_MMU_RADIX that we can then attach > with future versions That's probably a good idea.
On Thu, 2017-02-23 at 14:43 +1100, David Gibson wrote: > On Mon, Feb 20, 2017 at 04:16:26PM +1100, Balbir Singh wrote: > > > > On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh > > wrote: > > > > > > POWER9 processors implement the mmu as defined in version 3.00 of > > > the ISA. > > > > > > Add a definition for this mmu model and set the POWER9 cpu model > > > to use > > > this mmu model. > > > > > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> > > > --- > > > target/ppc/cpu-qom.h | 5 ++++- > > > target/ppc/mmu_helper.c | 2 ++ > > > target/ppc/translate_init.c | 3 +-- > > > 3 files changed, 7 insertions(+), 3 deletions(-) > > > > > > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h > > > index b7977ba..4e3132b 100644 > > > --- a/target/ppc/cpu-qom.h > > > +++ b/target/ppc/cpu-qom.h > > > @@ -86,10 +86,13 @@ enum powerpc_mmu_t { > > > POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > > > | POWERPC_MMU_64K > > > | POWERPC_MMU_AMR | 0x00000004, > > > - /* FIXME Add POWERPC_MMU_3_OO defines */ > > > /* Architecture 2.07 "degraded" (no 1T > > > segments) */ > > > POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR > > > | 0x00000004, > > > + /* Architecture 3.00 > > > variant */ > > > + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > > > + | POWERPC_MMU_64K > > > + | POWERPC_MMU_AMR | 0x00000005, > > I wonder if we need a POWERPC_MMU_RADIX that we can then attach > > with future versions > That's probably a good idea. > As discussed on IRC, will add an mmu feature flag POWERPC_MMU_V3
diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index b7977ba..4e3132b 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -86,10 +86,13 @@ enum powerpc_mmu_t { POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG | POWERPC_MMU_64K | POWERPC_MMU_AMR | 0x00000004, - /* FIXME Add POWERPC_MMU_3_OO defines */ /* Architecture 2.07 "degraded" (no 1T segments) */ POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR | 0x00000004, + /* Architecture 3.00 variant */ + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG + | POWERPC_MMU_64K + | POWERPC_MMU_AMR | 0x00000005, }; /*****************************************************************************/ diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index f746f53..172a305 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -1935,6 +1935,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: + case POWERPC_MMU_3_00: #endif /* defined(TARGET_PPC64) */ env->tlb_need_flush = 0; tlb_flush(CPU(cpu)); @@ -1974,6 +1975,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr) case POWERPC_MMU_2_06a: case POWERPC_MMU_2_07: case POWERPC_MMU_2_07a: + case POWERPC_MMU_3_00: /* tlbie invalidate TLBs for all segments */ /* XXX: given the fact that there are too many segments to invalidate, * and we still don't have a tlb_flush_mask(env, n, mask) in QEMU, diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c index 76f79fa..84bf125 100644 --- a/target/ppc/translate_init.c +++ b/target/ppc/translate_init.c @@ -8816,8 +8816,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) (1ull << MSR_PMM) | (1ull << MSR_RI) | (1ull << MSR_LE); - /* Using 2.07 defines until new radix model is added. */ - pcc->mmu_model = POWERPC_MMU_2_07; + pcc->mmu_model = POWERPC_MMU_3_00; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; /* segment page size remain the same */
POWER9 processors implement the mmu as defined in version 3.00 of the ISA. Add a definition for this mmu model and set the POWER9 cpu model to use this mmu model. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> --- target/ppc/cpu-qom.h | 5 ++++- target/ppc/mmu_helper.c | 2 ++ target/ppc/translate_init.c | 3 +-- 3 files changed, 7 insertions(+), 3 deletions(-)