From patchwork Thu Feb 16 20:27:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sylvain Lemieux X-Patchwork-Id: 728900 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vPSQZ6Dbyz9s85 for ; Fri, 17 Feb 2017 07:28:06 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="GIqGkOeP"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933158AbdBPU2D (ORCPT ); Thu, 16 Feb 2017 15:28:03 -0500 Received: from mail-it0-f68.google.com ([209.85.214.68]:36666 "EHLO mail-it0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932955AbdBPU2B (ORCPT ); Thu, 16 Feb 2017 15:28:01 -0500 Received: by mail-it0-f68.google.com with SMTP id g67so796193itb.3; Thu, 16 Feb 2017 12:28:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VhclGwlp21S6CdmervGUbcxmPZSHcGAgKd0oMwlK3LI=; b=GIqGkOeP+t5yy43BYT5oGZ0g8k54RFiQPmq67ylFyRLtN337H0EVWf4OfNuTkLqZaj 5csfz2dRjkDP1TuXBY4vObuREl86sKzJ29I3dAPKqkjOqJukdm9tKah6LrGYtuncbMe6 1+y7hjV/Z0R+OSyT5nCKsqqxcU30uUS/P4M+oVUoO7t8fFN7miOsBXah/PRN1ySGawae B3R8lb7p8H2HpXshd/yp4yya8yQcWDEbmPzz+C1xQdh9T0uojNIQAdBS1v6D4jYKTiIo S80BwOrrPrORx0aJt1dppjgLBuzjGIkhGAYdQG0vXETyMMT/rRw3kKHjsSNQIU0kFLKt XlBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VhclGwlp21S6CdmervGUbcxmPZSHcGAgKd0oMwlK3LI=; b=s7Q87K5PnjTUuulFio6eVOyGoVEdMB6MhI4e8iNqE7JyfuxzVlql4mRALw+BlOIVHx hR23ytJeiUqGV9Sd7msQK3IUY7JXmrEoKYZXgvxeXF2XuEcode5fO08zc1Nvj8Nr24UN GHYzowzB1DX13qO6IzNAz6k+gbWY9I3g+bgNyhMz+Ysrxr7ljV0uD3h9m2PPkiYLOCBM TCJ/Y+hS4RAQ4BX+QRW0o907+ojhsbCn+uhzfZU7VhPNkrrp1QE9Bum8cpyeB8rxp04C FYgWcrFHmOvEDSfCVOU45I+tgZKokBQRyjAoIEMmqELktgAm4ABL2SN3DhanICZF5Gu2 HYSw== X-Gm-Message-State: AMke39m72u6xTFlpn9SYablrOHfBjas0SC5BPhFqaAyfvdmuWgVjxCgMipiWUPid6I1yBw== X-Received: by 10.36.196.86 with SMTP id v83mr3927048itf.64.1487276880236; Thu, 16 Feb 2017 12:28:00 -0800 (PST) Received: from CABRO3AP00510.localdomain ([74.51.240.241]) by smtp.gmail.com with ESMTPSA id j19sm4684528iti.3.2017.02.16.12.27.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Feb 2017 12:27:59 -0800 (PST) From: slemieux.tyco@gmail.com To: thierry.reding@gmail.com, robh+dt@kernel.org, vz@mleia.com Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [RESEND PATCH 1/3] dt: pwm: lpc32xx: add description of clocks and #pwm-cells properties Date: Thu, 16 Feb 2017 15:27:47 -0500 Message-Id: <20170216202749.20653-2-slemieux.tyco@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170216202749.20653-1-slemieux.tyco@gmail.com> References: <20170216202749.20653-1-slemieux.tyco@gmail.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Vladimir Zapolskiy NXP LPC32xx SoCs have two simple independent PWM controllers with a single output each, in this case there is no need to specify PWM channel argument on client side, one cell for setting PWM output frequency is sufficient. Another added to the description property 'clocks' has a standard meaning of a controller supply clock, in the LPC32xx User's Manual the clock is denoted as PWM1_CLK or PWM2_CLK clock. Signed-off-by: Vladimir Zapolskiy Reviewed-by: Sylvain Lemieux Acked-by: Rob Herring --- Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt index 74b5bc5dd19a..523d79662861 100644 --- a/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/lpc32xx-pwm.txt @@ -3,15 +3,22 @@ LPC32XX PWM controller Required properties: - compatible: should be "nxp,lpc3220-pwm" - reg: physical base address and length of the controller's registers +- clocks: clock phandle and clock specifier pair +- #pwm-cells: should be 1, the cell is used to specify the period in + nanoseconds. Examples: pwm@4005c000 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005c000 0x4>; + clocks = <&clk LPC32XX_CLK_PWM1>; + #pwm-cells = <1>; }; pwm@4005c004 { compatible = "nxp,lpc3220-pwm"; reg = <0x4005c004 0x4>; + clocks = <&clk LPC32XX_CLK_PWM2>; + #pwm-cells = <1>; };