Message ID | 1290538431-13170-6-git-send-email-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show |
On Tue, Nov 23, 2010 at 06:53:44PM +0000, Peter Maydell wrote: > Fix errors in the decoding of the Neon forms of fixed-point VCVT: > * fixed-point VCVT is op 14 and 15, not 15 and 16 > * the fbits immediate field was being misinterpreted > * the sense of the to_fixed bit was inverted > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com> -Nathan
diff --git a/target-arm/translate.c b/target-arm/translate.c index 07a51ab..6c19f97 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -4850,11 +4850,15 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn) } neon_store_reg64(cpu_V0, rd + pass); } - } else if (op == 15 || op == 16) { + } else if (op >= 14) { /* VCVT fixed-point. */ + /* We have already masked out the must-be-1 top bit of imm6, + * hence this 32-shift where the ARM ARM has 64-imm6. + */ + shift = 32 - shift; for (pass = 0; pass < (q ? 4 : 2); pass++) { tcg_gen_ld_f32(cpu_F0s, cpu_env, neon_reg_offset(rm, pass)); - if (op & 1) { + if (!(op & 1)) { if (u) gen_vfp_ulto(0, shift); else
Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target-arm/translate.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-)