From patchwork Fri Feb 10 09:04:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lombard X-Patchwork-Id: 726444 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vKTYl06L9z9s2G for ; Fri, 10 Feb 2017 20:05:31 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3vKTYk6PkJzDqJp for ; Fri, 10 Feb 2017 20:05:30 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3vKTYF0J34zDqHh for ; Fri, 10 Feb 2017 20:05:04 +1100 (AEDT) Received: from pps.filterd (m0098393.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.20/8.16.0.20) with SMTP id v1A8xOTC003969 for ; Fri, 10 Feb 2017 04:05:03 -0500 Received: from e06smtp11.uk.ibm.com (e06smtp11.uk.ibm.com [195.75.94.107]) by mx0a-001b2d01.pphosted.com with ESMTP id 28gp6ggtuv-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Fri, 10 Feb 2017 04:05:02 -0500 Received: from localhost by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Fri, 10 Feb 2017 09:04:57 -0000 Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by d06dlp03.portsmouth.uk.ibm.com (Postfix) with ESMTP id 0FCD51B08023 for ; Fri, 10 Feb 2017 09:07:46 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id v1A94QXF60031046; Fri, 10 Feb 2017 09:04:26 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9D97DA405E; Fri, 10 Feb 2017 09:04:22 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id EBDDAA405B; Fri, 10 Feb 2017 09:04:21 +0000 (GMT) Received: from lombard-w520.ibm.com (unknown [9.164.182.111]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 10 Feb 2017 09:04:21 +0000 (GMT) From: Christophe Lombard To: skiboot@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com, imunsie@au1.ibm.com, andrew.donnellan@au1.ibm.com, christophe_lombard@fr.ibm.com Date: Fri, 10 Feb 2017 10:04:19 +0100 X-Mailer: git-send-email 2.7.4 In-Reply-To: <1486717462-5016-1-git-send-email-clombard@linux.vnet.ibm.com> References: <1486717462-5016-1-git-send-email-clombard@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 X-Content-Scanned: Fidelis XPS MAILER x-cbid: 17021009-0040-0000-0000-00000344D23C X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17021009-0041-0000-0000-00001EDA6CD2 Message-Id: <1486717462-5016-2-git-send-email-clombard@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-02-10_03:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 malwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1612050000 definitions=main-1702100090 Subject: [Skiboot] [PATCH 1/4] capi: Externalize capp timebase synchronization X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Externalize the chiptod code. this code will be common for PHB3 and PHB4. The reference to the structure PHB3 is remove and new arguments appear due to specific address registers. Signed-off-by: Christophe Lombard Reviewed-by: Andrew Donnellan --- hw/chiptod.c | 40 ++++++++++++++++++---------------------- hw/phb3.c | 2 +- include/chiptod.h | 4 ++-- 3 files changed, 21 insertions(+), 25 deletions(-) diff --git a/hw/chiptod.c b/hw/chiptod.c index 16dd0ae..746876a 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -21,10 +21,8 @@ #include #include #include -#include #include #include -#include #include #include #include @@ -1792,7 +1790,7 @@ void chiptod_init(void) /* CAPP timebase sync */ -static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset) +static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t tfmr_addr, uint32_t offset) { uint64_t tfmr; unsigned long timeout = 0; @@ -1808,12 +1806,12 @@ static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset) tfmr |= SPR_TFMR_TFMR_CORRUPT; /* Write CAPP TFMR */ - xscom_write(chip_id, CAPP_TFMR + offset, tfmr); + xscom_write(chip_id, tfmr_addr + offset, tfmr); /* We have to write "Clear TB Errors" again */ tfmr = base_tfmr | SPR_TFMR_CLEAR_TB_ERRORS; /* Write CAPP TFMR */ - xscom_write(chip_id, CAPP_TFMR + offset, tfmr); + xscom_write(chip_id, tfmr_addr + offset, tfmr); do { if (++timeout >= TIMEOUT_LOOPS) { @@ -1821,7 +1819,7 @@ static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset) return false; } /* Read CAPP TFMR */ - xscom_read(chip_id, CAPP_TFMR + offset, &tfmr); + xscom_read(chip_id, tfmr_addr + offset, &tfmr); if (tfmr & SPR_TFMR_TFMR_CORRUPT) { prerror("CAPP: TB error reset: corrupt TFMR!\n"); return false; @@ -1830,20 +1828,20 @@ static bool chiptod_capp_reset_tb_errors(uint32_t chip_id, uint32_t offset) return true; } -static bool chiptod_capp_mod_tb(uint32_t chip_id, uint32_t offset) +static bool chiptod_capp_mod_tb(uint32_t chip_id, uint32_t tfmr_addr, uint32_t offset) { uint64_t timeout = 0; uint64_t tfmr; /* Switch CAPP timebase to "Not Set" state */ tfmr = base_tfmr | SPR_TFMR_LOAD_TOD_MOD; - xscom_write(chip_id, CAPP_TFMR + offset, tfmr); + xscom_write(chip_id, tfmr_addr + offset, tfmr); do { if (++timeout >= (TIMEOUT_LOOPS*2)) { prerror("CAPP: TB \"Not Set\" timeout\n"); return false; } - xscom_read(chip_id, CAPP_TFMR + offset, &tfmr); + xscom_read(chip_id, tfmr_addr + offset, &tfmr); if (tfmr & SPR_TFMR_TFMR_CORRUPT) { prerror("CAPP: TB \"Not Set\" TFMR corrupt\n"); return false; @@ -1878,7 +1876,7 @@ static bool chiptod_wait_for_chip_sync(void) return true; } -static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t offset) +static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t tfmr_addr, uint32_t offset) { uint64_t tfmr; uint64_t timeout = 0; @@ -1889,7 +1887,7 @@ static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t offset) prerror("CAPP: TB Invalid!\n"); return false; } - xscom_read(chip_id, CAPP_TFMR + offset, &tfmr); + xscom_read(chip_id, tfmr_addr + offset, &tfmr); if (tfmr & SPR_TFMR_TFMR_CORRUPT) { prerror("CAPP: TFMR corrupt!\n"); return false; @@ -1898,25 +1896,23 @@ static bool chiptod_capp_check_tb_running(uint32_t chip_id, uint32_t offset) return true; } -bool chiptod_capp_timebase_sync(struct phb3 *p) +bool chiptod_capp_timebase_sync(unsigned int chip_id, uint32_t tfmr_addr, + uint32_t tb_addr, uint32_t offset) { uint64_t tfmr; uint64_t capp_tb; int64_t delta; - uint32_t offset; unsigned int retry = 0; - offset = PHB3_CAPP_REG_OFFSET(p); - /* Set CAPP TFMR to base tfmr value */ - xscom_write(p->chip_id, CAPP_TFMR + offset, base_tfmr); + xscom_write(chip_id, tfmr_addr + offset, base_tfmr); /* Reset CAPP TB errors before attempting the sync */ - if (!chiptod_capp_reset_tb_errors(p->chip_id, offset)) + if (!chiptod_capp_reset_tb_errors(chip_id, tfmr_addr, offset)) return false; /* Switch CAPP TB to "Not Set" state */ - if (!chiptod_capp_mod_tb(p->chip_id, offset)) + if (!chiptod_capp_mod_tb(chip_id, tfmr_addr, offset)) return false; /* Sync CAPP TB with core TB, retry while difference > 16usecs */ @@ -1928,19 +1924,19 @@ bool chiptod_capp_timebase_sync(struct phb3 *p) /* Make CAPP ready to get the TB, wait for chip sync */ tfmr = base_tfmr | SPR_TFMR_MOVE_CHIP_TOD_TO_TB; - xscom_write(p->chip_id, CAPP_TFMR + offset, tfmr); + xscom_write(chip_id, tfmr_addr + offset, tfmr); if (!chiptod_wait_for_chip_sync()) return false; /* Set CAPP TB from core TB */ - xscom_write(p->chip_id, CAPP_TB + offset, mftb()); + xscom_write(chip_id, tb_addr + offset, mftb()); /* Wait for CAPP TFMR tb_valid bit */ - if (!chiptod_capp_check_tb_running(p->chip_id, offset)) + if (!chiptod_capp_check_tb_running(chip_id, tfmr_addr, offset)) return false; /* Read CAPP TB, read core TB, compare */ - xscom_read(p->chip_id, CAPP_TB + offset, &capp_tb); + xscom_read(chip_id, tb_addr + offset, &capp_tb); delta = mftb() - capp_tb; if (delta < 0) delta = -delta; diff --git a/hw/phb3.c b/hw/phb3.c index e246e46..4010739 100644 --- a/hw/phb3.c +++ b/hw/phb3.c @@ -3577,7 +3577,7 @@ static int64_t enable_capi_mode(struct phb3 *p, uint64_t pe_number, bool dma_mod phb3_init_capp_regs(p, dma_mode); - if (!chiptod_capp_timebase_sync(p)) { + if (!chiptod_capp_timebase_sync(p->chip_id, CAPP_TFMR, CAPP_TB, PHB3_CAPP_REG_OFFSET(p))) { PHBERR(p, "CAPP: Failed to sync timebase\n"); return OPAL_HARDWARE; } diff --git a/include/chiptod.h b/include/chiptod.h index 64df8bc..fd5cd96 100644 --- a/include/chiptod.h +++ b/include/chiptod.h @@ -32,7 +32,7 @@ extern bool chiptod_wakeup_resync(void); extern int chiptod_recover_tb_errors(void); extern void chiptod_reset_tb(void); extern bool chiptod_adjust_topology(enum chiptod_topology topo, bool enable); -struct phb3; -extern bool chiptod_capp_timebase_sync(struct phb3 *p); +extern bool chiptod_capp_timebase_sync(unsigned int chip_id, uint32_t tfmr_addr, + uint32_t tb_addr, uint32_t offset); #endif /* __CHIPTOD_H */