From patchwork Tue Feb 7 23:04:07 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuriy Kolerov X-Patchwork-Id: 725437 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from bombadil.infradead.org (bombadil.infradead.org [65.50.211.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3vJ0Kh3fjWz9ryb for ; Wed, 8 Feb 2017 10:04:56 +1100 (AEDT) Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux)) id 1cbEog-0003VG-Vb; Tue, 07 Feb 2017 23:04:54 +0000 Received: from us01smtprelay-2.synopsys.com ([198.182.47.9] helo=smtprelay.synopsys.com) by bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux)) id 1cbEoN-0002nN-Rj for linux-snps-arc@lists.infradead.org; Tue, 07 Feb 2017 23:04:47 +0000 Received: from mailhost.synopsys.com (mailhost1.synopsys.com [10.12.238.239]) by smtprelay.synopsys.com (Postfix) with ESMTP id 8F76124E0487; Tue, 7 Feb 2017 15:04:14 -0800 (PST) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 49860D88; Tue, 7 Feb 2017 15:04:14 -0800 (PST) Received: from ykolerov-vm.internal.synopsys.com (ykolerov-840g3.internal.synopsys.com [10.225.2.62]) by mailhost.synopsys.com (Postfix) with ESMTP id B869BD5A; Tue, 7 Feb 2017 15:04:12 -0800 (PST) From: Yuriy Kolerov To: linux-snps-arc@lists.infradead.org Subject: [PATCH] ARCv2: intc: Disable all core interrupts by default Date: Wed, 8 Feb 2017 02:04:07 +0300 Message-Id: <1486508647-5997-1-git-send-email-yuriy.kolerov@synopsys.com> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20170207_150436_766475_2C1AB72B X-CRM114-Status: UNSURE ( 8.31 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.1 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [198.182.47.9 listed in list.dnswl.org] -0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay domain -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-snps-arc@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: Linux on Synopsys ARC Processors List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marc.zyngier@arm.com, Vineet.Gupta1@synopsys.com, Alexey.Brodkin@synopsys.com, linux-kernel@vger.kernel.org, Yuriy Kolerov MIME-Version: 1.0 Sender: "linux-snps-arc" Errors-To: linux-snps-arc-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org The kernel emits a lot of warnings about unexpected IRQs when an appropriate driver is not presented. It happens because all interrupts in the core controller are enabled by default after reset. It would be wise to keep all interrupts masked by default. Thus disable all local and common interrupts. If CPU consists of only 1 core without IDU then it is necessary to disable all interrupts in the core interrupt controller. If CPU contains IDU it means that there are may be more than 1 cores and common interrupts (>= FIRST_EXT_IRQ) must be disabled in IDU. Signed-off-by: Yuriy Kolerov --- arch/arc/kernel/intc-arcv2.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arc/kernel/intc-arcv2.c b/arch/arc/kernel/intc-arcv2.c index f928795..ac84d09 100644 --- a/arch/arc/kernel/intc-arcv2.c +++ b/arch/arc/kernel/intc-arcv2.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #define NR_EXCEPTIONS 16 @@ -34,6 +35,7 @@ void arc_init_IRQ(void) { unsigned int tmp, irq_prio, i; struct bcr_irq_arcv2 irq_bcr; + struct mcip_bcr mp; struct aux_irq_ctrl { #ifdef CONFIG_CPU_BIG_ENDIAN @@ -75,10 +77,27 @@ void arc_init_IRQ(void) * Set a default priority for all available interrupts to prevent * switching of register banks if Fast IRQ and multiple register banks * are supported by CPU. + * + * Disable all local and common interrupts. If CPU consists of only 1 + * core without IDU then it is necessary to disable all interrupts + * in the core interrupt controller. If CPU contains IDU it means that + * there are may be more than 1 cores and common interrupts + * (>= FIRST_EXT_IRQ) must be disabled in IDU. */ + + READ_BCR(ARC_REG_MCIP_BCR, mp); + for (i = NR_EXCEPTIONS; i < irq_bcr.irqs + NR_EXCEPTIONS; i++) { write_aux_reg(AUX_IRQ_SELECT, i); write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO); + + /* + * If IDU exists then all common interrupts >= FIRST_EXT_IRQ + * are masked by IDU thus disable only local interrupts (below + * FIRST_EXT_IRQ). Otherwise disable all interrupts. + */ + if (!mp.idu || i < FIRST_EXT_IRQ) + write_aux_reg(AUX_IRQ_ENABLE, 0); } /* setup status32, don't enable intr yet as kernel doesn't want */