From patchwork Tue Feb 7 17:50:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 725242 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vHsNG3M9sz9s2Q for ; Wed, 8 Feb 2017 04:51:42 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="EEAkCez9"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754831AbdBGRv3 (ORCPT ); Tue, 7 Feb 2017 12:51:29 -0500 Received: from mail-lf0-f66.google.com ([209.85.215.66]:35416 "EHLO mail-lf0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753587AbdBGRv0 (ORCPT ); Tue, 7 Feb 2017 12:51:26 -0500 Received: by mail-lf0-f66.google.com with SMTP id v186so7321766lfa.2; Tue, 07 Feb 2017 09:51:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SfF79TZLqYf741Jm/DENiGqo9wm88eDJnpZYaHyf8tI=; b=EEAkCez9clXg/G4y0M1sz1PSqCZuGKlFyE+tqbyD/VefaA+3lEcLtpspV1apXa4Bia K1C1ZA7tHFkhjROaGlNMnjgnwatjRea/QhXhG6wObx232V7327rQ0QDvlZBoTe+WF32o Ya1W6KCIS8nQx4yldKRKQMdLquw2bEHzrW0yEDPxDfhQjyZq5Pc4pT5jVUyyKcMVf/xX l5j+vw/UvgLIWSm/LeKq6oESAEu3a8OHkjGRqUB/ywdwAiAWogFSKvnQ4+3XMOxM8G3a AhUbcN3FCeC1D5x6CMIpdElMif3hSXs8WOrN/E2O+0wQG7TV4VL8E6V8GPzp7xKUhsQY lMoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SfF79TZLqYf741Jm/DENiGqo9wm88eDJnpZYaHyf8tI=; b=rypeDTA3IXs+DgALX/7rGDfvwjMIOOO5JCjvBGE3rk0xWZJVaeRMdLFgm1HDRsoSnM U5ymZCOHG0ASBC0AgERLtuUvMIrObCnHQUtlF7UOO2i0ubBrDMtYv0CqE57ssyec1lXh 6cWmeCfGNB3JKpAWRrk7Atukujt2gI1BtAYGpTTAsUDmZtTboFeokXIsECOBGqFuLi3d j9rT+Njtq1R9wIvN7xT5tk3TpUa8czvJowH2/5b4yTQBdxieXJpQCO+MdEtTpw00YDNx Y+IlFos83tN847Em5ExZQZFpSaGTHGFiJiX1oTN+IFyLppRd2OVzYRwhG2P/B2O8dJyE qhhA== X-Gm-Message-State: AIkVDXKewd2U/m8neCsVJ+y5G2d/NSYIU7k6/ordoxcWsM4TujPTtk3goiPHP2UoMqYSMw== X-Received: by 10.25.28.199 with SMTP id c190mr6055559lfc.173.1486489874355; Tue, 07 Feb 2017 09:51:14 -0800 (PST) Received: from hp-envy-1014.local (mm-104-154-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.154.104]) by smtp.gmail.com with ESMTPSA id y26sm70430lja.48.2017.02.07.09.51.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 07 Feb 2017 09:51:13 -0800 (PST) From: lis8215@gmail.com To: linux-sunxi@googlegroups.com Cc: thierry.reding@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Siarhei Volkau Subject: [PATCH v2 3/4] ARM: pwm: sun6i: add support the Allwinner A31 PWM. Date: Tue, 7 Feb 2017 20:50:45 +0300 Message-Id: <1486489846-662-4-git-send-email-lis8215@gmail.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1486489846-662-1-git-send-email-lis8215@gmail.com> References: <1486489846-662-1-git-send-email-lis8215@gmail.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Siarhei Volkau This patch introduce the sun6i PWM driver itself: - sun6i register operations, - sun6i prescaler table, - DT bindings for A31 SoC, - documentation update. Signed-off-by: Siarhei Volkau Acked-by: Rob Herring --- .../devicetree/bindings/pwm/pwm-sun4i.txt | 3 +- drivers/pwm/pwm-sun4i.c | 71 ++++++++++++++++++++++ 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt index f1cbeef..b737934 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt @@ -1,10 +1,11 @@ -Allwinner sun4i and sun7i SoC PWM controller +Allwinner sun4i, sun6i and sun7i SoC PWM controller Required properties: - compatible: should be one of: - "allwinner,sun4i-a10-pwm" - "allwinner,sun5i-a10s-pwm" - "allwinner,sun5i-a13-pwm" + - "allwinner,sun6i-a31-pwm" - "allwinner,sun7i-a20-pwm" - "allwinner,sun8i-h3-pwm" - reg: physical base address and length of the controller's registers diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 39912fc..0c1c372 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -47,6 +47,12 @@ #define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET)) +#define SUN6I_PWM_RDY_BIT PWM_RDY_BASE +#define SUN6I_PWM_CTL_OFFS 0x0 +#define SUN6I_PWM_PRD_OFFS 0x4 +#define SUN6I_PWM_CH_CTL(ch) (0x10 * (ch) + SUN6I_PWM_CTL_OFFS) +#define SUN6I_PWM_CH_PRD(ch) (0x10 * (ch) + SUN6I_PWM_PRD_OFFS) + struct sun4i_pwm_chip; static const u32 sun4i_prescaler_table[] = { @@ -68,6 +74,25 @@ static const u32 sun4i_prescaler_table[] = { 0, /* Actually 1 but tested separately */ }; +static const u32 sun6i_prescaler_table[] = { + 1, + 2, + 4, + 8, + 16, + 32, + 64, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + struct sunxi_reg_ops { int (*ctl_rdy)(struct sun4i_pwm_chip *chip, int npwm); u32 (*ctl_read)(struct sun4i_pwm_chip *chip, int npwm); @@ -140,6 +165,33 @@ static void sun4i_reg_prd_write(struct sun4i_pwm_chip *chip, int npwm, u32 val) sun4i_pwm_writel(chip, val, PWM_CH_PRD(npwm)); } +static int sun6i_reg_ctl_rdy(struct sun4i_pwm_chip *chip, int npwm) +{ + u32 val = sun4i_pwm_readl(chip, SUN6I_PWM_CH_CTL(npwm)); + + return val & BIT(SUN6I_PWM_RDY_BIT); +} + +static u32 sun6i_reg_ctl_read(struct sun4i_pwm_chip *chip, int npwm) +{ + return sun4i_pwm_readl(chip, SUN6I_PWM_CH_CTL(npwm)); +} + +static void sun6i_reg_ctl_write(struct sun4i_pwm_chip *chip, int npwm, u32 val) +{ + return sun4i_pwm_writel(chip, val, SUN6I_PWM_CH_CTL(npwm)); +} + +static u32 sun6i_reg_prd_read(struct sun4i_pwm_chip *chip, int npwm) +{ + return sun4i_pwm_readl(chip, SUN6I_PWM_CH_PRD(npwm)); +} + +static void sun6i_reg_prd_write(struct sun4i_pwm_chip *chip, int npwm, u32 val) +{ + return sun4i_pwm_writel(chip, val, SUN6I_PWM_CH_PRD(npwm)); +} + static int sun4i_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { @@ -306,6 +358,14 @@ static const struct sunxi_reg_ops sun4i_reg_ops = { .prd_write = sun4i_reg_prd_write, }; +static const struct sunxi_reg_ops sun6i_reg_ops = { + .ctl_rdy = sun6i_reg_ctl_rdy, + .ctl_read = sun6i_reg_ctl_read, + .ctl_write = sun6i_reg_ctl_write, + .prd_read = sun6i_reg_prd_read, + .prd_write = sun6i_reg_prd_write, +}; + static const struct pwm_ops sun4i_pwm_ops = { .config = sun4i_pwm_config, .set_polarity = sun4i_pwm_set_polarity, @@ -338,6 +398,14 @@ static const struct sun4i_pwm_data sun4i_pwm_data_a13 = { .prescaler_table = sun4i_prescaler_table, }; +static const struct sun4i_pwm_data sun6i_pwm_data_a31 = { + .has_prescaler_bypass = false, + .has_rdy = true, + .npwm = 4, + .ops = &sun6i_reg_ops, + .prescaler_table = sun6i_prescaler_table, +}; + static const struct sun4i_pwm_data sun4i_pwm_data_a20 = { .has_prescaler_bypass = true, .has_rdy = true, @@ -365,6 +433,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { .compatible = "allwinner,sun5i-a13-pwm", .data = &sun4i_pwm_data_a13, }, { + .compatible = "allwinner,sun6i-a31-pwm", + .data = &sun6i_pwm_data_a31, + }, { .compatible = "allwinner,sun7i-a20-pwm", .data = &sun4i_pwm_data_a20, }, {