From patchwork Fri Nov 19 23:20:18 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Williamson X-Patchwork-Id: 72331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B02F61007D2 for ; Sat, 20 Nov 2010 10:26:24 +1100 (EST) Received: from localhost ([127.0.0.1]:41194 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PJaL1-0003CE-KS for incoming@patchwork.ozlabs.org; Fri, 19 Nov 2010 18:25:51 -0500 Received: from [140.186.70.92] (port=57806 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PJaFk-0000tn-3e for qemu-devel@nongnu.org; Fri, 19 Nov 2010 18:20:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PJaFi-0001gq-Pe for qemu-devel@nongnu.org; Fri, 19 Nov 2010 18:20:23 -0500 Received: from mx1.redhat.com ([209.132.183.28]:16832) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PJaFi-0001gm-EC for qemu-devel@nongnu.org; Fri, 19 Nov 2010 18:20:22 -0500 Received: from int-mx02.intmail.prod.int.phx2.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id oAJNKL7B023980 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Fri, 19 Nov 2010 18:20:21 -0500 Received: from s20.home (ovpn01.gateway.prod.ext.phx2.redhat.com [10.5.9.1]) by int-mx02.intmail.prod.int.phx2.redhat.com (8.13.8/8.13.8) with ESMTP id oAJNKIK4007246; Fri, 19 Nov 2010 18:20:18 -0500 From: Alex Williamson To: kvm@vger.kernel.org, mst@redhat.com Date: Fri, 19 Nov 2010 16:20:18 -0700 Message-ID: <20101119232010.22162.60425.stgit@s20.home> In-Reply-To: <20101119231138.22162.93647.stgit@s20.home> References: <20101119231138.22162.93647.stgit@s20.home> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.67 on 10.5.11.12 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. Cc: chrisw@redhat.com, alex.williamson@redhat.com, qemu-devel@nongnu.org Subject: [Qemu-devel] [PATCH v3 6/9] device-assignment: Move PCI capabilities to match physical hardware X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Now that common PCI code doesn't have a hangup on capabilities being contiguous, move assigned device capabilities to match their offset on physical hardware. This helps for drivers that assume a capability configuration and don't bother searching. We can also remove several calls to assigned_dev_pci_read_* because we're overlaying the capability at the same location as the initial copy we made of config space. We can therefore just use pci_get_*. Signed-off-by: Alex Williamson --- hw/device-assignment.c | 65 +++++++++++++++--------------------------------- 1 files changed, 20 insertions(+), 45 deletions(-) diff --git a/hw/device-assignment.c b/hw/device-assignment.c index 975d3cb..6314773 100644 --- a/hw/device-assignment.c +++ b/hw/device-assignment.c @@ -366,16 +366,6 @@ static uint8_t assigned_dev_pci_read_byte(PCIDevice *d, int pos) return (uint8_t)assigned_dev_pci_read(d, pos, 1); } -static uint16_t assigned_dev_pci_read_word(PCIDevice *d, int pos) -{ - return (uint16_t)assigned_dev_pci_read(d, pos, 2); -} - -static uint32_t assigned_dev_pci_read_long(PCIDevice *d, int pos) -{ - return assigned_dev_pci_read(d, pos, 4); -} - static uint8_t pci_find_cap_offset(PCIDevice *d, uint8_t cap) { int id; @@ -1285,6 +1275,7 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev) { AssignedDevice *dev = container_of(pci_dev, AssignedDevice, dev); PCIRegion *pci_region = dev->real_device.regions; + int pos; /* Clear initial capabilities pointer and status copied from hw */ pci_set_byte(pci_dev->config + PCI_CAPABILITY_LIST, 0); @@ -1296,60 +1287,44 @@ static int assigned_device_pci_cap_init(PCIDevice *pci_dev) #ifdef KVM_CAP_DEVICE_MSI /* Expose MSI capability * MSI capability is the 1st capability in capability config */ - if (pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSI)) { - int vpos, ppos; - uint16_t flags; - + if ((pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSI))) { dev->cap.available |= ASSIGNED_DEVICE_CAP_MSI; - vpos = pci_add_capability(pci_dev, PCI_CAP_ID_MSI, 0, - PCI_CAPABILITY_CONFIG_MSI_LENGTH); - - memset(pci_dev->config + vpos + PCI_CAP_FLAGS, 0, - PCI_CAPABILITY_CONFIG_MSI_LENGTH - PCI_CAP_FLAGS); + pci_add_capability(pci_dev, PCI_CAP_ID_MSI, pos, + PCI_CAPABILITY_CONFIG_MSI_LENGTH); /* Only 32-bit/no-mask currently supported */ - ppos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSI); - flags = assigned_dev_pci_read_word(pci_dev, ppos + PCI_MSI_FLAGS); - flags &= PCI_MSI_FLAGS_QMASK; - pci_set_word(pci_dev->config + vpos + PCI_MSI_FLAGS, flags); + pci_set_word(pci_dev->config + pos + PCI_MSI_FLAGS, + pci_get_word(pci_dev->config + pos + PCI_MSI_FLAGS) & + PCI_MSI_FLAGS_QMASK); + pci_set_long(pci_dev->config + pos + PCI_MSI_ADDRESS_LO, 0); + pci_set_word(pci_dev->config + pos + PCI_MSI_DATA_32, 0); /* Set writable fields */ - pci_set_word(pci_dev->wmask + vpos + PCI_MSI_FLAGS, + pci_set_word(pci_dev->wmask + pos + PCI_MSI_FLAGS, PCI_MSI_FLAGS_QSIZE | PCI_MSI_FLAGS_ENABLE); - pci_set_long(pci_dev->wmask + vpos + PCI_MSI_ADDRESS_LO, 0xfffffffc); - pci_set_long(pci_dev->wmask + vpos + PCI_MSI_DATA_32, 0xffff); + pci_set_long(pci_dev->wmask + pos + PCI_MSI_ADDRESS_LO, 0xfffffffc); + pci_set_word(pci_dev->wmask + pos + PCI_MSI_DATA_32, 0xffff); } #endif #ifdef KVM_CAP_DEVICE_MSIX /* Expose MSI-X capability */ - if (pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSIX)) { - int vpos, ppos, entry_nr, bar_nr; + if ((pos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSIX))) { + int bar_nr; uint32_t msix_table_entry; dev->cap.available |= ASSIGNED_DEVICE_CAP_MSIX; - vpos = pci_add_capability(pci_dev, PCI_CAP_ID_MSIX, 0, + pci_add_capability(pci_dev, PCI_CAP_ID_MSIX, pos, PCI_CAPABILITY_CONFIG_MSIX_LENGTH); - memset(pci_dev->config + vpos + PCI_CAP_FLAGS, 0, - PCI_CAPABILITY_CONFIG_MSIX_LENGTH - PCI_CAP_FLAGS); + pci_set_word(pci_dev->config + pos + PCI_MSIX_FLAGS, + pci_get_word(pci_dev->config + pos + PCI_MSIX_FLAGS) & + PCI_MSIX_TABSIZE); /* Only enable and function mask bits are writable */ - pci_set_word(pci_dev->wmask + vpos + PCI_MSIX_FLAGS, + pci_set_word(pci_dev->wmask + pos + PCI_MSIX_FLAGS, PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); - ppos = pci_find_cap_offset(pci_dev, PCI_CAP_ID_MSIX); - - entry_nr = assigned_dev_pci_read_word(pci_dev, ppos + PCI_MSIX_FLAGS); - entry_nr &= PCI_MSIX_TABSIZE; - pci_set_word(pci_dev->config + vpos + PCI_MSIX_FLAGS, entry_nr); - - msix_table_entry = assigned_dev_pci_read_long(pci_dev, - ppos + PCI_MSIX_TABLE); - pci_set_long(pci_dev->config + vpos + PCI_MSIX_TABLE, msix_table_entry); - - pci_set_long(pci_dev->config + vpos + PCI_MSIX_PBA, - assigned_dev_pci_read_long(pci_dev, ppos + PCI_MSIX_PBA)); - + msix_table_entry = pci_get_long(pci_dev->config + pos + PCI_MSIX_TABLE); bar_nr = msix_table_entry & PCI_MSIX_BIR; msix_table_entry &= ~PCI_MSIX_BIR; dev->msix_table_addr = pci_region[bar_nr].base_addr + msix_table_entry;