| Message ID | alpine.LSU.2.20.1702012242040.2585@anthias.pfeifer.com |
|---|---|
| State | New |
| Headers | show |
On Wed, Feb 01, 2017 at 10:44:10PM +0100, Gerald Pfeifer wrote: > Hi Andi, or Uros, > > I am not sure, but got a pointer off-list. Is the patch below > appropriate, or is the term "lock critical section" a special > one for x86? Hi Gerald, The patch is ok. Lock critical region isn't a special term. -Andi > > Gerald > > Index: extend.texi > =================================================================== > --- extend.texi (revision 245106) > +++ extend.texi (working copy) > @@ -10103,7 +10103,7 @@ > @section x86-Specific Memory Model Extensions for Transactional Memory > > The x86 architecture supports additional memory ordering flags > -to mark lock critical sections for hardware lock elision. > +to mark critical sections for hardware lock elision. > These must be specified in addition to an existing memory order to > atomic intrinsics. > >
Index: extend.texi =================================================================== --- extend.texi (revision 245106) +++ extend.texi (working copy) @@ -10103,7 +10103,7 @@ @section x86-Specific Memory Model Extensions for Transactional Memory The x86 architecture supports additional memory ordering flags -to mark lock critical sections for hardware lock elision. +to mark critical sections for hardware lock elision. These must be specified in addition to an existing memory order to atomic intrinsics.